<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22001">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/cannonlake_rvp: Modify memory parameters for U-LP4 board<br><br>Drop the support for Cannonlake U DDR4 board, instead of that will<br>support Cannonlake U LPDDR4 platform.<br><br>TEST=Able to boot up on CNL U-LP4 RVP.<br><br>Change-Id: I2a3dd39875705dcb93a60ceba7c143e3e5328148<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/mainboard/intel/cannonlake_rvp/romstage.c<br>M src/mainboard/intel/cannonlake_rvp/spd/spd_util.c<br>2 files changed, 10 insertions(+), 34 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/22001/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/cannonlake_rvp/romstage.c b/src/mainboard/intel/cannonlake_rvp/romstage.c<br>index 03c5807..e0699da 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/romstage.c<br>+++ b/src/mainboard/intel/cannonlake_rvp/romstage.c<br>@@ -36,18 +36,10 @@<br> mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);<br> mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);<br> <br>- if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) {<br>- mem_cfg->DqPinsInterleaved = 1;<br>- mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA VREF_DQ_B->CHB */<br>- spd_index = 1;<br>- } else { /* For CONFIG_BOARD_INTEL_CANNONLAKE_RVPY */<br>- mem_cfg->DqPinsInterleaved = 0;<br>- mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */<br>- mem_cfg->ECT = 1; /* Early Command Training Enabled */<br>- spd_index = 2;<br>- }<br>-<br>- printk(BIOS_DEBUG,"SPD INDEX =0x%u\n", spd_index);<br>+ mem_cfg->DqPinsInterleaved = 0;<br>+ mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */<br>+ mem_cfg->ECT = 1; /* Early Command Training Enabled */<br>+ spd_index = 2;<br> <br> struct region_device spd_rdev;<br> <br>diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c<br>index 1e95280..4e2f31f 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c<br>+++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c<br>@@ -31,25 +31,17 @@<br> <br> void mainboard_fill_dq_map_ch1(void *dq_map_ptr)<br> {<br>- /* DQ byte map Ch1 */<br>- const u8 dq_map_u[12] = {<br>- 0x33, 0xCC, 0x33, 0xCC, 0xFF, 0x00,<br>- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };<br>-<br>- const u8 dq_map_y[12] = {<br>+ const u8 dq_map[12] = {<br> 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,<br> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };<br> <br>- if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))<br>- memcpy(dq_map_ptr, dq_map_u, sizeof(dq_map_u));<br>- else<br>- memcpy(dq_map_ptr, dq_map_y, sizeof(dq_map_y));<br>+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));<br> }<br> <br> void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)<br> {<br> /* DQS CPU<>DRAM map Ch0 */<br>- const u8 dqs_map_u[8] = { 0, 1, 3, 2, 4, 5, 6, 7 };<br>+ const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };<br> <br> const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };<br> <br>@@ -62,7 +54,7 @@<br> void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)<br> {<br> /* DQS CPU<>DRAM map Ch1 */<br>- const u8 dqs_map_u[8] = { 1, 0, 4, 5, 2, 3, 6, 7 };<br>+ const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };<br> <br> const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };<br> <br>@@ -82,16 +74,8 @@<br> void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)<br> {<br> /* Rcomp target */<br>- static const u16 RcompTarget_U[RCOMP_TARGET_PARAMS] = {<br>- 100, 33, 32, 33, 28 };<br>-<br>- static const u16 RcompTarget_Y[RCOMP_TARGET_PARAMS] = {<br>+ static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {<br> 80, 40, 40, 40, 30 };<br> <br>- if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))<br>- memcpy(rcomp_strength_ptr, RcompTarget_U,<br>- sizeof(RcompTarget_U));<br>- else<br>- memcpy(rcomp_strength_ptr, RcompTarget_Y,<br>- sizeof(RcompTarget_Y));<br>+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/22001">change 22001</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22001"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2a3dd39875705dcb93a60ceba7c143e3e5328148 </div>
<div style="display:none"> Gerrit-Change-Number: 22001 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Hannah Williams <hannah.williams@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: John Zhao <john.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Shaunak Saha <shaunak.saha@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>