[coreboot-gerrit] Change in coreboot[master]: Soc/intel/cannonlake: Add IGD Support and pre-OS display code
Abhay Kumar (Code Review)
gerrit at coreboot.org
Fri Oct 13 00:01:32 CEST 2017
Abhay Kumar has uploaded this change for review. ( https://review.coreboot.org/21999
Change subject: Soc/intel/cannonlake: Add IGD Support and pre-OS display code
......................................................................
Soc/intel/cannonlake: Add IGD Support and pre-OS display code
1. Add IGD opregion initialization.
2. Use frame buffer return by FSP for display.
TEST=Pre-OS screen comes up and VBT is getting passed to kernel.
Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
A src/soc/intel/cannonlake/graphics.c
3 files changed, 115 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/21999/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 774fe41..ddc24dd 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -61,6 +61,7 @@
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
+ select SOC_INTEL_COMMON_GFX_OPREGION
select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
select SOC_INTEL_COMMON_RESET
select SSE2
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 6fcee31..b9420aa 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -31,6 +31,7 @@
ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += gpio.c
+ramstage-y += graphics.c
ramstage-y += gspi.c
ramstage-y += gpio.c
ramstage-y += lpc.c
diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c
new file mode 100644
index 0000000..973c709
--- /dev/null
+++ b/src/soc/intel/cannonlake/graphics.c
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016-2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/pci_devs.h>
+#include <soc/intel/common/opregion.h>
+
+uintptr_t fsp_soc_get_igd_bar(void)
+{
+ device_t dev = SA_DEV_IGD;
+
+ /* Check if IGD PCI device is disabled */
+ if (!dev->enabled)
+ return 0;
+
+ return find_resource(dev, PCI_BASE_ADDRESS_2)->base;
+}
+
+static void igd_set_resources(struct device *dev)
+{
+ pci_dev_set_resources(dev);
+}
+
+static unsigned long igd_write_opregion(device_t dev, unsigned long current,
+ struct acpi_rsdp *rsdp)
+{
+ igd_opregion_t *opregion;
+ uint16_t reg16;
+
+ printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
+ opregion = (igd_opregion_t *)current;
+
+ if (init_igd_opregion(opregion) != CB_SUCCESS)
+ return current;
+
+ current += sizeof(igd_opregion_t);
+
+ /* TODO Initialize Mailbox 3 */
+ opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
+ opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
+ opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
+ opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
+ opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
+ opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
+ opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
+ opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
+ opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
+ opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
+ opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
+ opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
+ opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
+ opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
+ opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
+
+ /*
+ * TODO This needs to happen in S3 resume, too.
+ * Maybe it should move to the finalize handler.
+ */
+
+ pci_write_config32(dev, ASLS, (uintptr_t)opregion);
+ reg16 = pci_read_config16(dev, SWSCI);
+ reg16 &= ~(1 << 0);
+ reg16 |= (1 << 15);
+ pci_write_config16(dev, SWSCI, reg16);
+
+ return acpi_align_current(current);
+}
+
+static const struct device_operations igd_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = igd_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = pci_dev_init,
+ .write_acpi_tables = igd_write_opregion,
+ .enable = DEVICE_NOOP
+};
+
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1,
+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2,
+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3,
+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4,
+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1,
+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2,
+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3,
+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4,
+ 0,
+};
+
+static const struct pci_driver integrated_graphics_driver __pci_driver = {
+ .ops = &igd_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
--
To view, visit https://review.coreboot.org/21999
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32
Gerrit-Change-Number: 21999
Gerrit-PatchSet: 1
Gerrit-Owner: Abhay Kumar <abhay2101 at gmail.com>
Gerrit-Reviewer: Abhay Kumar <abhay.kumar at intel.com>
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