<p>Abhay Kumar has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21999">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Soc/intel/cannonlake: Add IGD Support and pre-OS display code<br><br>1. Add IGD opregion initialization.<br>2. Use frame buffer return by FSP for display.<br><br>TEST=Pre-OS screen comes up and VBT is getting passed to kernel.<br><br>Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32<br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>A src/soc/intel/cannonlake/graphics.c<br>3 files changed, 115 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/21999/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig<br>index 774fe41..ddc24dd 100644<br>--- a/src/soc/intel/cannonlake/Kconfig<br>+++ b/src/soc/intel/cannonlake/Kconfig<br>@@ -61,6 +61,7 @@<br> select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP<br> select SOC_INTEL_COMMON_BLOCK_TIMER<br> select SOC_INTEL_COMMON_BLOCK_UART<br>+ select SOC_INTEL_COMMON_GFX_OPREGION<br> select SOC_INTEL_COMMON_SPI_FLASH_PROTECT<br> select SOC_INTEL_COMMON_RESET<br> select SSE2<br>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 6fcee31..b9420aa 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -31,6 +31,7 @@<br> ramstage-y += chip.c<br> ramstage-y += cpu.c<br> ramstage-y += gpio.c<br>+ramstage-y += graphics.c<br> ramstage-y += gspi.c<br> ramstage-y += gpio.c<br> ramstage-y += lpc.c<br>diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c<br>new file mode 100644<br>index 0000000..973c709<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/graphics.c<br>@@ -0,0 +1,113 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2016-2017 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/acpi.h><br>+#include <arch/acpigen.h><br>+#include <console/console.h><br>+#include <fsp/util.h><br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <device/pci_ids.h><br>+#include <soc/pci_devs.h><br>+#include <soc/intel/common/opregion.h><br>+<br>+uintptr_t fsp_soc_get_igd_bar(void)<br>+{<br>+ device_t dev = SA_DEV_IGD;<br>+<br>+ /* Check if IGD PCI device is disabled */<br>+ if (!dev->enabled)<br>+ return 0;<br>+<br>+ return find_resource(dev, PCI_BASE_ADDRESS_2)->base;<br>+}<br>+<br>+static void igd_set_resources(struct device *dev)<br>+{<br>+ pci_dev_set_resources(dev);<br>+}<br>+<br>+static unsigned long igd_write_opregion(device_t dev, unsigned long current,<br>+ struct acpi_rsdp *rsdp)<br>+{<br>+ igd_opregion_t *opregion;<br>+ uint16_t reg16;<br>+<br>+ printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");<br>+ opregion = (igd_opregion_t *)current;<br>+<br>+ if (init_igd_opregion(opregion) != CB_SUCCESS)<br>+ return current;<br>+<br>+ current += sizeof(igd_opregion_t);<br>+<br>+ /* TODO Initialize Mailbox 3 */<br>+ opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;<br>+ opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;<br>+ opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */<br>+ opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;<br>+ opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;<br>+ opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;<br>+ opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;<br>+ opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;<br>+ opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;<br>+ opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;<br>+ opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;<br>+ opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;<br>+ opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;<br>+ opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;<br>+ opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;<br>+<br>+ /*<br>+ * TODO This needs to happen in S3 resume, too.<br>+ * Maybe it should move to the finalize handler.<br>+ */<br>+<br>+ pci_write_config32(dev, ASLS, (uintptr_t)opregion);<br>+ reg16 = pci_read_config16(dev, SWSCI);<br>+ reg16 &= ~(1 << 0);<br>+ reg16 |= (1 << 15);<br>+ pci_write_config16(dev, SWSCI, reg16);<br>+<br>+ return acpi_align_current(current);<br>+}<br>+<br>+static const struct device_operations igd_ops = {<br>+ .read_resources = pci_dev_read_resources,<br>+ .set_resources = igd_set_resources,<br>+ .enable_resources = pci_dev_enable_resources,<br>+ .init = pci_dev_init,<br>+ .write_acpi_tables = igd_write_opregion,<br>+ .enable = DEVICE_NOOP<br>+};<br>+<br>+static const unsigned short pci_device_ids[] = {<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3,<br>+ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4,<br>+ 0,<br>+};<br>+<br>+static const struct pci_driver integrated_graphics_driver __pci_driver = {<br>+ .ops = &igd_ops,<br>+ .vendor = PCI_VENDOR_ID_INTEL,<br>+ .devices = pci_device_ids,<br>+};<br></pre><p>To view, visit <a href="https://review.coreboot.org/21999">change 21999</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32 </div>
<div style="display:none"> Gerrit-Change-Number: 21999 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Abhay Kumar <abhay2101@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Abhay Kumar <abhay.kumar@intel.com> </div>