[coreboot-gerrit] Change in coreboot[master]: (WIP) soc/amd/common: Enable PSP in SMM
frank vibrans (Code Review)
gerrit at coreboot.org
Thu Oct 12 18:36:41 CEST 2017
frank vibrans has uploaded this change for review. ( https://review.coreboot.org/21991
Change subject: (WIP) soc/amd/common: Enable PSP in SMM
......................................................................
(WIP) soc/amd/common: Enable PSP in SMM
Install BIOS-to-PSP communications for SMM. The BIOS-to-PSP
communications requires a command/response buffer in SMM space
after BIOS boot complete that is provided by this code.
Change-Id: I50565d6e4e694f542bccb9f5f24b294454d3a37f
Signed-off-by: Frank Vibrans <frank.vibrans at scarletltd.com>
---
M src/soc/amd/common/block/include/amdblocks/psp.h
M src/soc/amd/common/block/psp/Makefile.inc
M src/soc/amd/common/block/psp/psp.c
3 files changed, 59 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/21991/1
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h
index 96b1a11..7915b1f 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp.h
@@ -18,8 +18,6 @@
#include <stdint.h>
#include <compiler.h>
-#include <Porting.h>
-#include <Proc/Psp/PspBaseLib/PspBaseLib.h>
/* x86 to PSP commands */
#define MBOX_BIOS_CMD_DRAM_INFO 0x01
@@ -114,6 +112,27 @@
#define PSP_INIT_TIMEOUT 10000 /* 10 seconds */
#define PSP_CMD_TIMEOUT 1000 /* 1 second */
+/* This set of definitions is copied from AMD's vendorcode/PspBaseLib.h
+ * which cannot be included in the SMM environment.
+ */
+#if ENV_SMM
+#define PSP_PCI_SEG 0x00 /* PSP Seg address */
+#define PSP_PCI_BUS 0x00 /* PSP Bus address */
+#define PSP_PCI_DEV 0x08 /* PSP Device address */
+#define PSP_PCI_FN 0x00 /* PSP Fn address */
+#define PSP_PCI_BDA ((PSP_PCI_DEV << 11) + (PSP_PCI_FN << 8))
+
+#define PSP_PCI_BAR3_REG 0x20 /* Pci Bar3 */
+#define PSP_PCI_EXTRAPCIHDR_REG 0x48 /* Extra PCI Header Ctr */
+
+/* PSP Private Block Base Address */
+#define PSP_MSR_PRIVATE_BLOCK_BAR 0xc00110a2
+#define PSP_MAILBOX_BASE 0x70 /* Mailbox base offset on BAR */
+
+/* This is a hack to provide a bogus prototype for compiling for SMM. */
+bool PspBarInitEarly(void);
+#endif
+
/* BIOS-to-PSP functions return 0 if successful, else negative value */
int psp_notify_dram(void);
int psp_notify_smm_info(uintptr_t base, size_t length, uintptr_t psp_data_base,
diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc
index eebba16..b4f3b8d 100644
--- a/src/soc/amd/common/block/psp/Makefile.inc
+++ b/src/soc/amd/common/block/psp/Makefile.inc
@@ -1,2 +1,3 @@
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c
+smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c
diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c
index ae90621..5bbdf41 100644
--- a/src/soc/amd/common/block/psp/psp.c
+++ b/src/soc/amd/common/block/psp/psp.c
@@ -14,11 +14,17 @@
*/
#include <stddef.h>
+#include <types.h>
#include <arch/io.h>
#include <timer.h>
+#include <cpu/x86/msr.h>
#include <device/pci_def.h>
#include <console/console.h>
#include <amdblocks/psp.h>
+#if !ENV_SMM
+# include <Porting.h>
+# include <Proc/Psp/PspBaseLib/PspBaseLib.h>
+#endif
static const char *psp_status_nobase = "error: PSP BAR3 not assigned";
static const char *psp_status_halted = "error: PSP in halted state";
@@ -48,16 +54,39 @@
}
}
+static bool get_psp_bar3addr(uint32_t *psp_mmio)
+{
+ msr_t psp_addr;
+ uint32_t pci_reg48;
+ uint32_t t_mmio = 0xffffffff;
+
+ pci_reg48 = pci_read_config32(PSP_DEV, PSP_PCI_EXTRAPCIHDR_REG);
+ if (pci_reg48 & BIT(12)) {
+ psp_addr = rdmsr(PSP_MSR_PRIVATE_BLOCK_BAR);
+ t_mmio = psp_addr.lo;
+ } else {
+ t_mmio = pci_read_config32(PSP_DEV, PSP_PCI_BAR3_REG) & 0xFFF00000;
+ }
+
+ if (t_mmio == 0xffffffff)
+ return false;
+
+ *psp_mmio = t_mmio;
+ return true;
+}
+
static struct psp_mbox *get_mbox_address(void)
{
- UINT32 base; /* UINT32 for compatibility with PspBaseLib */
- BOOLEAN bar3_status;
+ uint32_t base;
+ bool bar3_status;
uintptr_t baseptr;
- bar3_status = GetPspBar3Addr(&base);
- if (!bar3_status) {
- PspBarInitEarly();
- bar3_status = GetPspBar3Addr(&base);
+ bar3_status = get_psp_bar3addr(&base);
+ if (!ENV_SMM) {
+ if (!bar3_status) {
+ PspBarInitEarly();
+ bar3_status = get_psp_bar3addr(&base);
+ }
}
if (!bar3_status)
return NULL;
@@ -194,7 +223,7 @@
printk(BIOS_DEBUG, "buffer status=0x%x ",
rd_resp_sts(&buffer));
if (cmd_status)
- printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status));
+ printk(BIOS_ERR, "%s\n", status_to_string(cmd_status));
else
printk(BIOS_DEBUG, "OK\n");
@@ -224,7 +253,7 @@
cmd_status = send_psp_command(MBOX_BIOS_CMD_SMM_INFO, &buffer);
if (cmd_status)
- printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status));
+ printk(BIOS_ERR, "%s\n", status_to_string(cmd_status));
else
printk(BIOS_DEBUG, "OK\n");
--
To view, visit https://review.coreboot.org/21991
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I50565d6e4e694f542bccb9f5f24b294454d3a37f
Gerrit-Change-Number: 21991
Gerrit-PatchSet: 1
Gerrit-Owner: frank vibrans <frank.vibrans at scarletltd.com>
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