[coreboot-gerrit] Change in coreboot[master]: Separate mainboard memory init from platform fsp memory init

[Gaggery Tsai (Code Review)]

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/21987


Change subject: Separate mainboard memory init from platform fsp memory init
......................................................................

Separate mainboard memory init from platform fsp memory init

This patch adds a API fucntion to separate mainboard memory init from
platform_fsp_memory_init_params_cb and skip the routine to get SPD when
system is resumed from S3 since MRC cahce is adopted and validated.

BUG=b:67021596
TEST=Run suspend/resume on Fizz and Poppy and make sure the systems are
	working well when system is resumed from S3.

Change-Id: I1692fca8456290d1471973b746537b5fec504e03
Signed-off-by: Gaggery Tsai <gaggery.tsai at intel.com>
---
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
3 files changed, 11 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/21987/1

diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 123db30..18de016 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -51,6 +51,7 @@
 
 /* Callbacks for updating stage-specific parameters */
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version);
+void platform_fsp_memory_init_params_mb(FSPM_UPD *mupd, bool s3wake);
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
 
 /*
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index b08ee1e..f7003b0 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -348,9 +348,12 @@
 					memmap) != CB_SUCCESS)
 		die("FSPM_ARCH_UPD not found!\n");
 
-	/* Give SoC and mainboard a chance to update the UPD */
+	/* Update the memory init parameters and FSPM test config */
 	platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version);
 
+	/* Give mainboard a chance to update the UPD */
+	platform_fsp_memory_init_params_mb(&fspm_upd, s3wake);
+
 	if (IS_ENABLED(CONFIG_MMA))
 		setup_mma(&fspm_upd.FspmConfig);
 
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index d4a5e34..703ed2a 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -241,8 +241,13 @@
 
 	/* Enable SMBus controller based on config */
 	m_cfg->SmbusEnable = config->SmbusEnable;
+}
 
-	mainboard_memory_init_params(mupd);
+void platform_fsp_memory_init_params_mb(FSPM_UPD *mupd, bool s3wake)
+{
+	/* Wd do not need to read SPD again when system is waken from S3 */
+	if (!s3wake)
+		mainboard_memory_init_params(mupd);
 }
 
 void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1692fca8456290d1471973b746537b5fec504e03
Gerrit-Change-Number: 21987
Gerrit-PatchSet: 1
Gerrit-Owner: Gaggery Tsai <gaggery.tsai at intel.com>
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