[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Use EBDA area to store cbmem_top address
Subrata Banik (Code Review)
gerrit at coreboot.org
Thu Oct 12 14:34:09 CEST 2017
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21985
Change subject: soc/intel/cannonlake: Use EBDA area to store cbmem_top address
......................................................................
soc/intel/cannonlake: Use EBDA area to store cbmem_top address
This patch uses BIOS EBDA area to store relevent details
like cbmem top during romstage after MRC init is done.
Also provide provision to use the same EBDA data across
various stages without reexecuting memory map algorithm.
BRANCH=none
BUG=b:63974384
TEST=Ensures HW based memmap algorithm is executing once in romstage
and store required data into EBDA for other stage to avoid redundant
calculation and get cbmem_top start from EBDA area.
Change-Id: I763ad8181396ea8d8c0d5cf088264791ba62dceb
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/include/soc/bootblock.h
A src/soc/intel/cannonlake/include/soc/ebda.h
M src/soc/intel/cannonlake/memmap.c
5 files changed, 77 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/21985/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 774fe41..3ce8776 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -46,6 +46,7 @@
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_CSE
+ select SOC_INTEL_COMMON_BLOCK_EBDA
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_GSPI
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 0062c0d..091e6f7 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -196,6 +196,4 @@
enable_rtc_upper_bank();
heci_init(HECI1_BASE_ADDRESS);
-
- clear_cbmem_top();
}
diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h
index fcef4ef..2a6ca1f 100644
--- a/src/soc/intel/cannonlake/include/soc/bootblock.h
+++ b/src/soc/intel/cannonlake/include/soc/bootblock.h
@@ -27,6 +27,4 @@
void pch_early_iorange_init(void);
void report_platform_info(void);
-void clear_cbmem_top(void);
-
#endif
diff --git a/src/soc/intel/cannonlake/include/soc/ebda.h b/src/soc/intel/cannonlake/include/soc/ebda.h
new file mode 100644
index 0000000..4cde5c0
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/ebda.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_EBDA_H
+#define SOC_EBDA_H
+
+struct ebda_config {
+ uint32_t signature; /* 0x00 - EBDA signature */
+ uint32_t tolum_base; /* 0x04 - coreboot memory start */
+};
+
+#endif
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index e5117ad..a8a8a3f 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -13,6 +13,8 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
+
+#include <arch/ebda.h>
#include <arch/io.h>
#include <cbmem.h>
#include <chip.h>
@@ -20,8 +22,8 @@
#include <device/device.h>
#include <device/pci.h>
#include <fsp/util.h>
+#include <intelblocks/ebda.h>
#include <intelblocks/systemagent.h>
-#include <soc/bootblock.h>
#include <soc/pci_devs.h>
#include <soc/smm.h>
#include <soc/systemagent.h>
@@ -79,20 +81,6 @@
*size = sub_size;
return 0;
-}
-
-static void *top_of_ram_register(void)
-{
- int num;
- int offset;
- num = (read32((uintptr_t *)HPET_BASE_ADDRESS) >> 8) & 0x1f;
- offset = 0x100 + (0x20 * num) + 0x08;
- return (void *)(uintptr_t)(HPET_BASE_ADDRESS + offset);
-}
-
-void clear_cbmem_top(void)
-{
- write32(top_of_ram_register(), 0);
}
static bool is_ptt_enable(void)
@@ -268,44 +256,62 @@
return dram_base;
}
-void cbmem_top_init(void)
+/* Fill up memory layout information */
+void fill_soc_memmap_ebda(struct ebda_config *cfg)
{
- uintptr_t top;
size_t chipset_mem_size;
- top = calculate_dram_base(&chipset_mem_size);
-
- write32(top_of_ram_register(), top);
+ cfg->tolum_base = calculate_dram_base(&chipset_mem_size);
}
+void cbmem_top_init(void)
+{
+ /* Fill up EBDA area */
+ fill_ebda_area();
+}
+
+/*
+ * +-------------------------+ Top of RAM (aligned)
+ * | System Management Mode |
+ * | code and data | Length: CONFIG_TSEG_SIZE
+ * | (TSEG) |
+ * +-------------------------+ SMM base (aligned)
+ * | |
+ * | Chipset Reserved Memory |
+ * | |
+ * +-------------------------+ top_of_ram (aligned)
+ * | |
+ * | CBMEM Root |
+ * | |
+ * +-------------------------+
+ * | |
+ * | FSP Reserved Memory |
+ * | |
+ * +-------------------------+
+ * | |
+ * | Various CBMEM Entries |
+ * | |
+ * +-------------------------+ top_of_stack (8 byte aligned)
+ * | |
+ * | stack (CBMEM Entry) |
+ * | |
+ * +-------------------------+
+ */
void *cbmem_top(void)
{
+ struct ebda_config ebda_cfg;
+ struct ebda_config *cfg = &ebda_cfg;
+
/*
- * +-------------------------+ Top of RAM (aligned)
- * | System Management Mode |
- * | code and data | Length: CONFIG_TSEG_SIZE
- * | (TSEG) |
- * +-------------------------+ SMM base (aligned)
- * | |
- * | Chipset Reserved Memory |
- * | |
- * +-------------------------+ top_of_ram (aligned)
- * | |
- * | CBMEM Root |
- * | |
- * +-------------------------+
- * | |
- * | FSP Reserved Memory |
- * | |
- * +-------------------------+
- * | |
- * | Various CBMEM Entries |
- * | |
- * +-------------------------+ top_of_stack (8 byte aligned)
- * | |
- * | stack (CBMEM Entry) |
- * | |
- * +-------------------------+
+ * Check if Tseg has been initialized, we will use this as a flag
+ * to check if the MRC is done, and only then continue to read the
+ * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before
+ * PRMRR_MASK MSR lock bit is set.
*/
- return (void *)(uintptr_t)read32(top_of_ram_register());
+ if (sa_get_tseg_base() == 0)
+ return NULL;
+
+ read_ebda_data(cfg, sizeof(*cfg));
+
+ return (void *)(uintptr_t)cfg->tolum_base;
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I763ad8181396ea8d8c0d5cf088264791ba62dceb
Gerrit-Change-Number: 21985
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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