<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21985">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Use EBDA area to store cbmem_top address<br><br>This patch uses BIOS EBDA area to store relevent details<br>like cbmem top during romstage after MRC init is done.<br>Also provide provision to use the same EBDA data across<br>various stages without reexecuting memory map algorithm.<br><br>BRANCH=none<br>BUG=b:63974384<br>TEST=Ensures HW based memmap algorithm is executing once in romstage<br>and store required data into EBDA for other stage to avoid redundant<br>calculation and get cbmem_top start from EBDA area.<br><br>Change-Id: I763ad8181396ea8d8c0d5cf088264791ba62dceb<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/bootblock/pch.c<br>M src/soc/intel/cannonlake/include/soc/bootblock.h<br>A src/soc/intel/cannonlake/include/soc/ebda.h<br>M src/soc/intel/cannonlake/memmap.c<br>5 files changed, 77 insertions(+), 50 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/21985/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig<br>index 774fe41..3ce8776 100644<br>--- a/src/soc/intel/cannonlake/Kconfig<br>+++ b/src/soc/intel/cannonlake/Kconfig<br>@@ -46,6 +46,7 @@<br> select SOC_INTEL_COMMON_BLOCK_CPU<br> select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT<br> select SOC_INTEL_COMMON_BLOCK_CSE<br>+ select SOC_INTEL_COMMON_BLOCK_EBDA<br> select SOC_INTEL_COMMON_BLOCK_FAST_SPI<br> select SOC_INTEL_COMMON_BLOCK_GPIO<br> select SOC_INTEL_COMMON_BLOCK_GSPI<br>diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c<br>index 0062c0d..091e6f7 100644<br>--- a/src/soc/intel/cannonlake/bootblock/pch.c<br>+++ b/src/soc/intel/cannonlake/bootblock/pch.c<br>@@ -196,6 +196,4 @@<br> enable_rtc_upper_bank();<br> <br> heci_init(HECI1_BASE_ADDRESS);<br>-<br>- clear_cbmem_top();<br> }<br>diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h<br>index fcef4ef..2a6ca1f 100644<br>--- a/src/soc/intel/cannonlake/include/soc/bootblock.h<br>+++ b/src/soc/intel/cannonlake/include/soc/bootblock.h<br>@@ -27,6 +27,4 @@<br> void pch_early_iorange_init(void);<br> void report_platform_info(void);<br> <br>-void clear_cbmem_top(void);<br>-<br> #endif<br>diff --git a/src/soc/intel/cannonlake/include/soc/ebda.h b/src/soc/intel/cannonlake/include/soc/ebda.h<br>new file mode 100644<br>index 0000000..4cde5c0<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/include/soc/ebda.h<br>@@ -0,0 +1,24 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef SOC_EBDA_H<br>+#define SOC_EBDA_H<br>+<br>+struct ebda_config {<br>+ uint32_t signature; /* 0x00 - EBDA signature */<br>+ uint32_t tolum_base; /* 0x04 - coreboot memory start */<br>+};<br>+<br>+#endif<br>diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c<br>index e5117ad..a8a8a3f 100644<br>--- a/src/soc/intel/cannonlake/memmap.c<br>+++ b/src/soc/intel/cannonlake/memmap.c<br>@@ -13,6 +13,8 @@<br> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br> * GNU General Public License for more details.<br> */<br>+<br>+#include <arch/ebda.h><br> #include <arch/io.h><br> #include <cbmem.h><br> #include <chip.h><br>@@ -20,8 +22,8 @@<br> #include <device/device.h><br> #include <device/pci.h><br> #include <fsp/util.h><br>+#include <intelblocks/ebda.h><br> #include <intelblocks/systemagent.h><br>-#include <soc/bootblock.h><br> #include <soc/pci_devs.h><br> #include <soc/smm.h><br> #include <soc/systemagent.h><br>@@ -79,20 +81,6 @@<br> *size = sub_size;<br> <br> return 0;<br>-}<br>-<br>-static void *top_of_ram_register(void)<br>-{<br>- int num;<br>- int offset;<br>- num = (read32((uintptr_t *)HPET_BASE_ADDRESS) >> 8) & 0x1f;<br>- offset = 0x100 + (0x20 * num) + 0x08;<br>- return (void *)(uintptr_t)(HPET_BASE_ADDRESS + offset);<br>-}<br>-<br>-void clear_cbmem_top(void)<br>-{<br>- write32(top_of_ram_register(), 0);<br> }<br> <br> static bool is_ptt_enable(void)<br>@@ -268,44 +256,62 @@<br> return dram_base;<br> }<br> <br>-void cbmem_top_init(void)<br>+/* Fill up memory layout information */<br>+void fill_soc_memmap_ebda(struct ebda_config *cfg)<br> {<br>- uintptr_t top;<br> size_t chipset_mem_size;<br> <br>- top = calculate_dram_base(&chipset_mem_size);<br>-<br>- write32(top_of_ram_register(), top);<br>+ cfg->tolum_base = calculate_dram_base(&chipset_mem_size);<br> }<br> <br>+void cbmem_top_init(void)<br>+{<br>+ /* Fill up EBDA area */<br>+ fill_ebda_area();<br>+}<br>+<br>+/*<br>+ * +-------------------------+ Top of RAM (aligned)<br>+ * | System Management Mode |<br>+ * | code and data | Length: CONFIG_TSEG_SIZE<br>+ * | (TSEG) |<br>+ * +-------------------------+ SMM base (aligned)<br>+ * | |<br>+ * | Chipset Reserved Memory |<br>+ * | |<br>+ * +-------------------------+ top_of_ram (aligned)<br>+ * | |<br>+ * | CBMEM Root |<br>+ * | |<br>+ * +-------------------------+<br>+ * | |<br>+ * | FSP Reserved Memory |<br>+ * | |<br>+ * +-------------------------+<br>+ * | |<br>+ * | Various CBMEM Entries |<br>+ * | |<br>+ * +-------------------------+ top_of_stack (8 byte aligned)<br>+ * | |<br>+ * | stack (CBMEM Entry) |<br>+ * | |<br>+ * +-------------------------+<br>+ */<br> void *cbmem_top(void)<br> {<br>+ struct ebda_config ebda_cfg;<br>+ struct ebda_config *cfg = &ebda_cfg;<br>+<br> /*<br>- * +-------------------------+ Top of RAM (aligned)<br>- * | System Management Mode |<br>- * | code and data | Length: CONFIG_TSEG_SIZE<br>- * | (TSEG) |<br>- * +-------------------------+ SMM base (aligned)<br>- * | |<br>- * | Chipset Reserved Memory |<br>- * | |<br>- * +-------------------------+ top_of_ram (aligned)<br>- * | |<br>- * | CBMEM Root |<br>- * | |<br>- * +-------------------------+<br>- * | |<br>- * | FSP Reserved Memory |<br>- * | |<br>- * +-------------------------+<br>- * | |<br>- * | Various CBMEM Entries |<br>- * | |<br>- * +-------------------------+ top_of_stack (8 byte aligned)<br>- * | |<br>- * | stack (CBMEM Entry) |<br>- * | |<br>- * +-------------------------+<br>+ * Check if Tseg has been initialized, we will use this as a flag<br>+ * to check if the MRC is done, and only then continue to read the<br>+ * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before<br>+ * PRMRR_MASK MSR lock bit is set.<br> */<br>- return (void *)(uintptr_t)read32(top_of_ram_register());<br>+ if (sa_get_tseg_base() == 0)<br>+ return NULL;<br>+<br>+ read_ebda_data(cfg, sizeof(*cfg));<br>+<br>+ return (void *)(uintptr_t)cfg->tolum_base;<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/21985">change 21985</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21985"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I763ad8181396ea8d8c0d5cf088264791ba62dceb </div>
<div style="display:none"> Gerrit-Change-Number: 21985 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>