[coreboot-gerrit] Change in coreboot[master]: mainboard/pcengines/apu2: add apu3 and apu5 variants
Kamil Wcisło (Code Review)
gerrit at coreboot.org
Thu Oct 12 12:02:13 CEST 2017
Kamil Wcisło has uploaded this change for review. ( https://review.coreboot.org/21981
Change subject: mainboard/pcengines/apu2: add apu3 and apu5 variants
......................................................................
mainboard/pcengines/apu2: add apu3 and apu5 variants
Apu3 and apu5 are additional variants of apu2 board.
Apu3 has no LPC connector exposed, but has additional USB header. It has
also 2 slots for SIM cards and one of the gpios is used to control
switching between them.
Apu5 is differing by having 6 SIM card slots (3 SIMSWAP switches).
This patch adds support for those other variants by not introducing
additional code redundancy.
Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0
Signed-off-by: Kamil Wcislo <kamil.wcislo at 3mdeb.com>
---
M src/mainboard/pcengines/apu2/BiosCallOuts.c
M src/mainboard/pcengines/apu2/Kconfig
M src/mainboard/pcengines/apu2/Kconfig.name
M src/mainboard/pcengines/apu2/Makefile.inc
M src/mainboard/pcengines/apu2/board_info.txt
M src/mainboard/pcengines/apu2/gpio_ftns.h
M src/mainboard/pcengines/apu2/romstage.c
R src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
A src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
A src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb
10 files changed, 249 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/21981/1
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
index 071de97..dafee10 100644
--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -90,8 +90,17 @@
/* EHCI configuration */
FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
- FchParams->Usb.Ehci1Enable = FALSE; // Disable EHCI 0 (port 0 to 3)
- FchParams->Usb.Ehci2Enable = TRUE; // Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
+
+#if IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2)
+ // Disable EHCI 0 (port 0 to 3)
+ FchParams->Usb.Ehci1Enable = FALSE;
+#else
+ // Enable EHCI 0 (port 0 to 3)
+ FchParams->Usb.Ehci1Enable = TRUE;
+#endif
+ // Enable EHCI 1 ( port 4 to 7)
+ // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
+ FchParams->Usb.Ehci2Enable = TRUE;
/* sata configuration */
FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
index cbcbb7c..3e83fb8 100644
--- a/src/mainboard/pcengines/apu2/Kconfig
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -14,7 +14,7 @@
# GNU General Public License for more details.
#
-if BOARD_PCENGINES_APU2
+if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU5
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -37,9 +37,21 @@
string
default pcengines/apu2
+config VARIANT_DIR
+ string
+ default "apu2" if BOARD_PCENGINES_APU2
+ default "apu3" if BOARD_PCENGINES_APU3
+ default "apu5" if BOARD_PCENGINES_APU5
+
+config DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
config MAINBOARD_PART_NUMBER
string
- default "apu2"
+ default "apu2" if BOARD_PCENGINES_APU2
+ default "apu3" if BOARD_PCENGINES_APU3
+ default "apu5" if BOARD_PCENGINES_APU5
config MAX_CPUS
int
diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name
index ab19ee4..68e6d6e 100644
--- a/src/mainboard/pcengines/apu2/Kconfig.name
+++ b/src/mainboard/pcengines/apu2/Kconfig.name
@@ -1,2 +1,8 @@
config BOARD_PCENGINES_APU2
bool "APU2"
+
+config BOARD_PCENGINES_APU3
+ bool "APU3"
+
+config BOARD_PCENGINES_APU5
+ bool "APU5"
diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc
index 3724b17..0e89740 100644
--- a/src/mainboard/pcengines/apu2/Makefile.inc
+++ b/src/mainboard/pcengines/apu2/Makefile.inc
@@ -24,3 +24,5 @@
# Order of names in SPD_SOURCES is important!
SPD_SOURCES = HYNIX-2G-1333
SPD_SOURCES += HYNIX-4G-1333-ECC
+
+subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/pcengines/apu2/board_info.txt b/src/mainboard/pcengines/apu2/board_info.txt
index a69e616..e21acef 100644
--- a/src/mainboard/pcengines/apu2/board_info.txt
+++ b/src/mainboard/pcengines/apu2/board_info.txt
@@ -1,4 +1,4 @@
-Board name: PC Engines APU2
+Board name: PC Engines APU2/3/5
Board URL: http://www.pcengines.ch/apu2c2.htm
Category: half
ROM protocol: SPI
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h
index 1813496..e08ee7b 100644
--- a/src/mainboard/pcengines/apu2/gpio_ftns.h
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.h
@@ -23,33 +23,36 @@
#define GPIO_OFFSET 0x1500
//
-// Based on PC Engines APU2C schematics
+// Based on PC Engines APU2C and APU3A schematics
// http://www.pcengines.ch/schema/apu2c.pdf
+// http://www.pcengines.ch/schema/apu3a.pdf
//
-#define IOMUX_GPIO_32 0x59 // MODESW
+#define IOMUX_GPIO_32 0x59 // MODESW (SIMSWAP2 on APU5)
+#define IOMUX_GPIO_33 0x5A // SIMSWAP (SIMSWAP3 on APU5)
#define IOMUX_GPIO_49 0x40 // STRAP0
#define IOMUX_GPIO_50 0x41 // STRAP1
-#define IOMUX_GPIO_51 0x42 // PE3 Reset
-#define IOMUX_GPIO_55 0x43 // PE4 Reset
+#define IOMUX_GPIO_51 0x42 // PE3 Reset (SIM1 Reset on APU5)
+#define IOMUX_GPIO_55 0x43 // PE4 Reset (SIM2 Reset on APU5)
#define IOMUX_GPIO_57 0x44 // LED1#
#define IOMUX_GPIO_58 0x45 // LED2#
#define IOMUX_GPIO_59 0x46 // LED3#
-#define IOMUX_GPIO_64 0x47 // PE3_WDIS
+#define IOMUX_GPIO_64 0x47 // PE3_WDIS (SIM3 Reset on APU5)
#define IOMUX_GPIO_66 0x5B // SPKR
-#define IOMUX_GPIO_68 0x48 // PE4_WDIS
+#define IOMUX_GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5)
#define IOMUX_GPIO_71 0x4D // PROCHOT
-#define GPIO_32 0x164 // MODESW
+#define GPIO_32 0x164 // MODESW (SIMSWAP2 on APU5)
+#define GPIO_33 0x168 // SIMSWAP (SIMSWAP3 on APU5)
#define GPIO_49 0x100 // STRAP0
#define GPIO_50 0x104 // STRAP1
-#define GPIO_51 0x108 // PE3 Reset
-#define GPIO_55 0x10C // PE4 Reset
+#define GPIO_51 0x108 // PE3 Reset (SIM1 Reset on APU5)
+#define GPIO_55 0x10C // PE4 Reset (SIM2 Reset on APU5)
#define GPIO_57 0x110 // LED1#
#define GPIO_58 0x114 // LED2#
#define GPIO_59 0x118 // LED3#
-#define GPIO_64 0x11C // PE3_WDIS
+#define GPIO_64 0x11C // PE3_WDIS (SIM3 Reset on APU5)
#define GPIO_66 0x16C // SPKR
-#define GPIO_68 0x120 // PE4_WDIS
+#define GPIO_68 0x120 // PE4_WDIS (SIMSWAP1 on APU5)
#define GPIO_71 0x134 // PROCHOT
#define GPIO_OUTPUT_ENABLE 23
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index 1ccf7c4..8e7786f 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -105,7 +105,10 @@
//
// Configure output disabled, value low, pull up/down disabled
//
+#if IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) || \
+ IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3)
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting);
+#endif
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting);
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting);
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting);
@@ -113,6 +116,10 @@
// Configure output enabled, value low, pull up/down disabled
//
setting = 0x1 << GPIO_OUTPUT_ENABLE;
+#if IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3)
+ configure_gpio(ACPI_MMIO_BASE,
+ IOMUX_GPIO_33, Function0, GPIO_33, setting);
+#endif
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting);
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting);
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting);
@@ -120,6 +127,12 @@
// Configure output enabled, value high, pull up/down disabled
//
setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE;
+#if IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)
+ configure_gpio(ACPI_MMIO_BASE,
+ IOMUX_GPIO_32, Function0, GPIO_32, setting);
+ configure_gpio(ACPI_MMIO_BASE,
+ IOMUX_GPIO_33, Function0, GPIO_33, setting);
+#endif
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting);
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting);
configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting);
diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
similarity index 100%
rename from src/mainboard/pcengines/apu2/devicetree.cb
rename to src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
new file mode 100644
index 0000000..880f3dd
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
@@ -0,0 +1,94 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2013 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/pi/00730F01/root_complex
+ device cpu_cluster 0 on
+ chip cpu/amd/pi/00730F01
+ device lapic 0 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+
+ chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 off end # IOMMU
+ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
+ device pci 1.1 off end # Internal Multimedia
+ device pci 2.0 on end # PCIe Host Bridge
+ device pci 2.1 on end # mPCIe slot 2 (on GFX lane)
+ device pci 2.2 on end # LAN3
+ device pci 2.3 on end # LAN2
+ device pci 2.4 on end # LAN1
+ device pci 2.5 on end # mPCIe slot 1
+ device pci 8.0 on end # Platform Security Processor
+ end #chip northbridge/amd/pi/00730F01
+
+ chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0 muxed with EHCI 2
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB EHCI0 usb[0:3] is connected
+ device pci 13.0 on end # USB EHCI1 usb[4:7]
+ device pci 14.0 on end # SM
+ device pci 14.3 on # LPC 0x439d
+ chip superio/nuvoton/nct5104d # SIO NCT5104D
+ register "irq_trigger_type" = "0"
+ device pnp 2e.0 off end
+ device pnp 2e.2 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.10 on
+ # UART C is conditionally turned on
+ io 0x60 = 0x3e8
+ irq 0x70 = 4
+ end
+ device pnp 2e.11 on
+ # UART D is conditionally turned on
+ io 0x60 = 0x2e8
+ irq 0x70 = 3
+ end
+ device pnp 2e.8 off end
+ device pnp 2e.f off end
+ # GPIO0 and GPIO1 are conditionally turned on
+ device pnp 2e.007 on end
+ device pnp 2e.107 on end
+ device pnp 2e.607 off end
+ device pnp 2e.e off end
+ end # SIO NCT5104D
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end # LPC TPM
+ end # LPC 0x439d
+
+ device pci 14.7 on end # SD
+ device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI
+ end #chip southbridge/amd/pi/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+ end #domain
+end #northbridge/amd/pi/00730F01/root_complex
diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb
new file mode 100644
index 0000000..880f3dd
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb
@@ -0,0 +1,94 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2013 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/pi/00730F01/root_complex
+ device cpu_cluster 0 on
+ chip cpu/amd/pi/00730F01
+ device lapic 0 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+
+ chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 off end # IOMMU
+ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
+ device pci 1.1 off end # Internal Multimedia
+ device pci 2.0 on end # PCIe Host Bridge
+ device pci 2.1 on end # mPCIe slot 2 (on GFX lane)
+ device pci 2.2 on end # LAN3
+ device pci 2.3 on end # LAN2
+ device pci 2.4 on end # LAN1
+ device pci 2.5 on end # mPCIe slot 1
+ device pci 8.0 on end # Platform Security Processor
+ end #chip northbridge/amd/pi/00730F01
+
+ chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0 muxed with EHCI 2
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB EHCI0 usb[0:3] is connected
+ device pci 13.0 on end # USB EHCI1 usb[4:7]
+ device pci 14.0 on end # SM
+ device pci 14.3 on # LPC 0x439d
+ chip superio/nuvoton/nct5104d # SIO NCT5104D
+ register "irq_trigger_type" = "0"
+ device pnp 2e.0 off end
+ device pnp 2e.2 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.10 on
+ # UART C is conditionally turned on
+ io 0x60 = 0x3e8
+ irq 0x70 = 4
+ end
+ device pnp 2e.11 on
+ # UART D is conditionally turned on
+ io 0x60 = 0x2e8
+ irq 0x70 = 3
+ end
+ device pnp 2e.8 off end
+ device pnp 2e.f off end
+ # GPIO0 and GPIO1 are conditionally turned on
+ device pnp 2e.007 on end
+ device pnp 2e.107 on end
+ device pnp 2e.607 off end
+ device pnp 2e.e off end
+ end # SIO NCT5104D
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end # LPC TPM
+ end # LPC 0x439d
+
+ device pci 14.7 on end # SD
+ device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI
+ end #chip southbridge/amd/pi/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+ end #domain
+end #northbridge/amd/pi/00730F01/root_complex
--
To view, visit https://review.coreboot.org/21981
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0
Gerrit-Change-Number: 21981
Gerrit-PatchSet: 1
Gerrit-Owner: Kamil Wcisło <kamil.wcislo at 3mdeb.com>
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