<p>Kamil Wcisło has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21981">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/pcengines/apu2: add apu3 and apu5 variants<br><br>Apu3 and apu5 are additional variants of apu2 board.<br>Apu3 has no LPC connector exposed, but has additional USB header. It has<br>also 2 slots for SIM cards and one of the gpios is used to control<br>switching between them.<br>Apu5 is differing by having 6 SIM card slots (3 SIMSWAP switches).<br><br>This patch adds support for those other variants by not introducing<br>additional code redundancy.<br><br>Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0<br>Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com><br>---<br>M src/mainboard/pcengines/apu2/BiosCallOuts.c<br>M src/mainboard/pcengines/apu2/Kconfig<br>M src/mainboard/pcengines/apu2/Kconfig.name<br>M src/mainboard/pcengines/apu2/Makefile.inc<br>M src/mainboard/pcengines/apu2/board_info.txt<br>M src/mainboard/pcengines/apu2/gpio_ftns.h<br>M src/mainboard/pcengines/apu2/romstage.c<br>R src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb<br>A src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb<br>A src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb<br>10 files changed, 249 insertions(+), 16 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/21981/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c<br>index 071de97..dafee10 100644<br>--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c<br>+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c<br>@@ -90,8 +90,17 @@<br> <br> /* EHCI configuration */<br> FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);<br>- FchParams->Usb.Ehci1Enable = FALSE; // Disable EHCI 0 (port 0 to 3)<br>- FchParams->Usb.Ehci2Enable = TRUE; // Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.<br>+<br>+#if IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2)<br>+ // Disable EHCI 0 (port 0 to 3)<br>+ FchParams->Usb.Ehci1Enable = FALSE;<br>+#else<br>+ // Enable EHCI 0 (port 0 to 3)<br>+ FchParams->Usb.Ehci1Enable = TRUE;<br>+#endif<br>+ // Enable EHCI 1 ( port 4 to 7)<br>+ // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.<br>+ FchParams->Usb.Ehci2Enable = TRUE;<br> <br> /* sata configuration */<br> FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP<br>diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig<br>index cbcbb7c..3e83fb8 100644<br>--- a/src/mainboard/pcengines/apu2/Kconfig<br>+++ b/src/mainboard/pcengines/apu2/Kconfig<br>@@ -14,7 +14,7 @@<br> # GNU General Public License for more details.<br> #<br> <br>-if BOARD_PCENGINES_APU2<br>+if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU5<br> <br> config BOARD_SPECIFIC_OPTIONS # dummy<br> def_bool y<br>@@ -37,9 +37,21 @@<br> string<br> default pcengines/apu2<br> <br>+config VARIANT_DIR<br>+ string<br>+ default "apu2" if BOARD_PCENGINES_APU2<br>+ default "apu3" if BOARD_PCENGINES_APU3<br>+ default "apu5" if BOARD_PCENGINES_APU5<br>+<br>+config DEVICETREE<br>+ string<br>+ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"<br>+<br> config MAINBOARD_PART_NUMBER<br> string<br>- default "apu2"<br>+ default "apu2" if BOARD_PCENGINES_APU2<br>+ default "apu3" if BOARD_PCENGINES_APU3<br>+ default "apu5" if BOARD_PCENGINES_APU5<br> <br> config MAX_CPUS<br> int<br>diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name<br>index ab19ee4..68e6d6e 100644<br>--- a/src/mainboard/pcengines/apu2/Kconfig.name<br>+++ b/src/mainboard/pcengines/apu2/Kconfig.name<br>@@ -1,2 +1,8 @@<br> config BOARD_PCENGINES_APU2<br> bool "APU2"<br>+<br>+config BOARD_PCENGINES_APU3<br>+ bool "APU3"<br>+<br>+config BOARD_PCENGINES_APU5<br>+ bool "APU5"<br>diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc<br>index 3724b17..0e89740 100644<br>--- a/src/mainboard/pcengines/apu2/Makefile.inc<br>+++ b/src/mainboard/pcengines/apu2/Makefile.inc<br>@@ -24,3 +24,5 @@<br> # Order of names in SPD_SOURCES is important!<br> SPD_SOURCES = HYNIX-2G-1333<br> SPD_SOURCES += HYNIX-4G-1333-ECC<br>+<br>+subdirs-y += variants/$(VARIANT_DIR)<br>diff --git a/src/mainboard/pcengines/apu2/board_info.txt b/src/mainboard/pcengines/apu2/board_info.txt<br>index a69e616..e21acef 100644<br>--- a/src/mainboard/pcengines/apu2/board_info.txt<br>+++ b/src/mainboard/pcengines/apu2/board_info.txt<br>@@ -1,4 +1,4 @@<br>-Board name: PC Engines APU2<br>+Board name: PC Engines APU2/3/5<br> Board URL: http://www.pcengines.ch/apu2c2.htm<br> Category: half<br> ROM protocol: SPI<br>diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h<br>index 1813496..e08ee7b 100644<br>--- a/src/mainboard/pcengines/apu2/gpio_ftns.h<br>+++ b/src/mainboard/pcengines/apu2/gpio_ftns.h<br>@@ -23,33 +23,36 @@<br> #define GPIO_OFFSET 0x1500<br> <br> //<br>-// Based on PC Engines APU2C schematics<br>+// Based on PC Engines APU2C and APU3A schematics<br> // http://www.pcengines.ch/schema/apu2c.pdf<br>+// http://www.pcengines.ch/schema/apu3a.pdf<br> //<br>-#define IOMUX_GPIO_32 0x59 // MODESW<br>+#define IOMUX_GPIO_32 0x59 // MODESW (SIMSWAP2 on APU5)<br>+#define IOMUX_GPIO_33 0x5A // SIMSWAP (SIMSWAP3 on APU5)<br> #define IOMUX_GPIO_49 0x40 // STRAP0<br> #define IOMUX_GPIO_50 0x41 // STRAP1<br>-#define IOMUX_GPIO_51 0x42 // PE3 Reset<br>-#define IOMUX_GPIO_55 0x43 // PE4 Reset<br>+#define IOMUX_GPIO_51 0x42 // PE3 Reset (SIM1 Reset on APU5)<br>+#define IOMUX_GPIO_55 0x43 // PE4 Reset (SIM2 Reset on APU5)<br> #define IOMUX_GPIO_57 0x44 // LED1#<br> #define IOMUX_GPIO_58 0x45 // LED2#<br> #define IOMUX_GPIO_59 0x46 // LED3#<br>-#define IOMUX_GPIO_64 0x47 // PE3_WDIS<br>+#define IOMUX_GPIO_64 0x47 // PE3_WDIS (SIM3 Reset on APU5)<br> #define IOMUX_GPIO_66 0x5B // SPKR<br>-#define IOMUX_GPIO_68 0x48 // PE4_WDIS<br>+#define IOMUX_GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5)<br> #define IOMUX_GPIO_71 0x4D // PROCHOT<br> <br>-#define GPIO_32 0x164 // MODESW<br>+#define GPIO_32 0x164 // MODESW (SIMSWAP2 on APU5)<br>+#define GPIO_33 0x168 // SIMSWAP (SIMSWAP3 on APU5)<br> #define GPIO_49 0x100 // STRAP0<br> #define GPIO_50 0x104 // STRAP1<br>-#define GPIO_51 0x108 // PE3 Reset<br>-#define GPIO_55 0x10C // PE4 Reset<br>+#define GPIO_51 0x108 // PE3 Reset (SIM1 Reset on APU5)<br>+#define GPIO_55 0x10C // PE4 Reset (SIM2 Reset on APU5)<br> #define GPIO_57 0x110 // LED1#<br> #define GPIO_58 0x114 // LED2#<br> #define GPIO_59 0x118 // LED3#<br>-#define GPIO_64 0x11C // PE3_WDIS<br>+#define GPIO_64 0x11C // PE3_WDIS (SIM3 Reset on APU5)<br> #define GPIO_66 0x16C // SPKR<br>-#define GPIO_68 0x120 // PE4_WDIS<br>+#define GPIO_68 0x120 // PE4_WDIS (SIMSWAP1 on APU5)<br> #define GPIO_71 0x134 // PROCHOT<br> <br> #define GPIO_OUTPUT_ENABLE 23<br>diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c<br>index 1ccf7c4..8e7786f 100644<br>--- a/src/mainboard/pcengines/apu2/romstage.c<br>+++ b/src/mainboard/pcengines/apu2/romstage.c<br>@@ -105,7 +105,10 @@<br> //<br> // Configure output disabled, value low, pull up/down disabled<br> //<br>+#if IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) || \<br>+ IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3)<br> configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting);<br>+#endif<br> configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting);<br> configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting);<br> configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting);<br>@@ -113,6 +116,10 @@<br> // Configure output enabled, value low, pull up/down disabled<br> //<br> setting = 0x1 << GPIO_OUTPUT_ENABLE;<br>+#if IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3)<br>+ configure_gpio(ACPI_MMIO_BASE,<br>+ IOMUX_GPIO_33, Function0, GPIO_33, setting);<br>+#endif<br> configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting);<br> configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting);<br> configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting);<br>@@ -120,6 +127,12 @@<br> // Configure output enabled, value high, pull up/down disabled<br> //<br> setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE;<br>+#if IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)<br>+ configure_gpio(ACPI_MMIO_BASE,<br>+ IOMUX_GPIO_32, Function0, GPIO_32, setting);<br>+ configure_gpio(ACPI_MMIO_BASE,<br>+ IOMUX_GPIO_33, Function0, GPIO_33, setting);<br>+#endif<br> configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting);<br> configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting);<br> configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting);<br>diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb<br>similarity index 100%<br>rename from src/mainboard/pcengines/apu2/devicetree.cb<br>rename to src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb<br>diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb<br>new file mode 100644<br>index 0000000..880f3dd<br>--- /dev/null<br>+++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb<br>@@ -0,0 +1,94 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2013 Advanced Micro Devices, Inc.<br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+chip northbridge/amd/pi/00730F01/root_complex<br>+ device cpu_cluster 0 on<br>+ chip cpu/amd/pi/00730F01<br>+ device lapic 0 on end<br>+ end<br>+ end<br>+<br>+ device domain 0 on<br>+ subsystemid 0x1022 0x1410 inherit<br>+ chip northbridge/amd/pi/00730F01 # CPU side of HT root complex<br>+<br>+ chip northbridge/amd/pi/00730F01 # PCI side of HT root complex<br>+ device pci 0.0 on end # Root Complex<br>+ device pci 0.2 off end # IOMMU<br>+ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804<br>+ device pci 1.1 off end # Internal Multimedia<br>+ device pci 2.0 on end # PCIe Host Bridge<br>+ device pci 2.1 on end # mPCIe slot 2 (on GFX lane)<br>+ device pci 2.2 on end # LAN3<br>+ device pci 2.3 on end # LAN2<br>+ device pci 2.4 on end # LAN1<br>+ device pci 2.5 on end # mPCIe slot 1<br>+ device pci 8.0 on end # Platform Security Processor<br>+ end #chip northbridge/amd/pi/00730F01<br>+<br>+ chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus<br>+ device pci 10.0 on end # XHCI HC0 muxed with EHCI 2<br>+ device pci 11.0 on end # SATA<br>+ device pci 12.0 on end # USB EHCI0 usb[0:3] is connected<br>+ device pci 13.0 on end # USB EHCI1 usb[4:7]<br>+ device pci 14.0 on end # SM<br>+ device pci 14.3 on # LPC 0x439d<br>+ chip superio/nuvoton/nct5104d # SIO NCT5104D<br>+ register "irq_trigger_type" = "0"<br>+ device pnp 2e.0 off end<br>+ device pnp 2e.2 on<br>+ io 0x60 = 0x3f8<br>+ irq 0x70 = 4<br>+ end<br>+ device pnp 2e.3 on<br>+ io 0x60 = 0x2f8<br>+ irq 0x70 = 3<br>+ end<br>+ device pnp 2e.10 on<br>+ # UART C is conditionally turned on<br>+ io 0x60 = 0x3e8<br>+ irq 0x70 = 4<br>+ end<br>+ device pnp 2e.11 on<br>+ # UART D is conditionally turned on<br>+ io 0x60 = 0x2e8<br>+ irq 0x70 = 3<br>+ end<br>+ device pnp 2e.8 off end<br>+ device pnp 2e.f off end<br>+ # GPIO0 and GPIO1 are conditionally turned on<br>+ device pnp 2e.007 on end<br>+ device pnp 2e.107 on end<br>+ device pnp 2e.607 off end<br>+ device pnp 2e.e off end<br>+ end # SIO NCT5104D<br>+ chip drivers/pc80/tpm<br>+ device pnp 0c31.0 on end<br>+ end # LPC TPM<br>+ end # LPC 0x439d<br>+<br>+ device pci 14.7 on end # SD<br>+ device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI<br>+ end #chip southbridge/amd/pi/hudson<br>+<br>+ device pci 18.0 on end<br>+ device pci 18.1 on end<br>+ device pci 18.2 on end<br>+ device pci 18.3 on end<br>+ device pci 18.4 on end<br>+ device pci 18.5 on end<br>+<br>+ end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex<br>+ end #domain<br>+end #northbridge/amd/pi/00730F01/root_complex<br>diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb<br>new file mode 100644<br>index 0000000..880f3dd<br>--- /dev/null<br>+++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb<br>@@ -0,0 +1,94 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2013 Advanced Micro Devices, Inc.<br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+chip northbridge/amd/pi/00730F01/root_complex<br>+ device cpu_cluster 0 on<br>+ chip cpu/amd/pi/00730F01<br>+ device lapic 0 on end<br>+ end<br>+ end<br>+<br>+ device domain 0 on<br>+ subsystemid 0x1022 0x1410 inherit<br>+ chip northbridge/amd/pi/00730F01 # CPU side of HT root complex<br>+<br>+ chip northbridge/amd/pi/00730F01 # PCI side of HT root complex<br>+ device pci 0.0 on end # Root Complex<br>+ device pci 0.2 off end # IOMMU<br>+ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804<br>+ device pci 1.1 off end # Internal Multimedia<br>+ device pci 2.0 on end # PCIe Host Bridge<br>+ device pci 2.1 on end # mPCIe slot 2 (on GFX lane)<br>+ device pci 2.2 on end # LAN3<br>+ device pci 2.3 on end # LAN2<br>+ device pci 2.4 on end # LAN1<br>+ device pci 2.5 on end # mPCIe slot 1<br>+ device pci 8.0 on end # Platform Security Processor<br>+ end #chip northbridge/amd/pi/00730F01<br>+<br>+ chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus<br>+ device pci 10.0 on end # XHCI HC0 muxed with EHCI 2<br>+ device pci 11.0 on end # SATA<br>+ device pci 12.0 on end # USB EHCI0 usb[0:3] is connected<br>+ device pci 13.0 on end # USB EHCI1 usb[4:7]<br>+ device pci 14.0 on end # SM<br>+ device pci 14.3 on # LPC 0x439d<br>+ chip superio/nuvoton/nct5104d # SIO NCT5104D<br>+ register "irq_trigger_type" = "0"<br>+ device pnp 2e.0 off end<br>+ device pnp 2e.2 on<br>+ io 0x60 = 0x3f8<br>+ irq 0x70 = 4<br>+ end<br>+ device pnp 2e.3 on<br>+ io 0x60 = 0x2f8<br>+ irq 0x70 = 3<br>+ end<br>+ device pnp 2e.10 on<br>+ # UART C is conditionally turned on<br>+ io 0x60 = 0x3e8<br>+ irq 0x70 = 4<br>+ end<br>+ device pnp 2e.11 on<br>+ # UART D is conditionally turned on<br>+ io 0x60 = 0x2e8<br>+ irq 0x70 = 3<br>+ end<br>+ device pnp 2e.8 off end<br>+ device pnp 2e.f off end<br>+ # GPIO0 and GPIO1 are conditionally turned on<br>+ device pnp 2e.007 on end<br>+ device pnp 2e.107 on end<br>+ device pnp 2e.607 off end<br>+ device pnp 2e.e off end<br>+ end # SIO NCT5104D<br>+ chip drivers/pc80/tpm<br>+ device pnp 0c31.0 on end<br>+ end # LPC TPM<br>+ end # LPC 0x439d<br>+<br>+ device pci 14.7 on end # SD<br>+ device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI<br>+ end #chip southbridge/amd/pi/hudson<br>+<br>+ device pci 18.0 on end<br>+ device pci 18.1 on end<br>+ device pci 18.2 on end<br>+ device pci 18.3 on end<br>+ device pci 18.4 on end<br>+ device pci 18.5 on end<br>+<br>+ end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex<br>+ end #domain<br>+end #northbridge/amd/pi/00730F01/root_complex<br></pre><p>To view, visit <a href="https://review.coreboot.org/21981">change 21981</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21981"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0 </div>
<div style="display:none"> Gerrit-Change-Number: 21981 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kamil Wcisło <kamil.wcislo@3mdeb.com> </div>