[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add GNVS variables and include SGX ASL

[Pratikkumar V Prajapati (Code Review)]

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21971


Change subject: soc/intel/skylake: Add GNVS variables and include SGX ASL
......................................................................

soc/intel/skylake: Add GNVS variables and include SGX ASL

- add GNVS variables for SGX
- include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set

Change-Id: Ie95eb79a01e1c0005e0f137b015b7fe000c1ab2a
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati at intel.com>
---
M src/soc/intel/skylake/acpi/globalnvs.asl
M src/soc/intel/skylake/acpi/pch.asl
M src/soc/intel/skylake/include/soc/nvs.h
3 files changed, 11 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/21971/1

diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index 8a7606c..5564f02 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -67,6 +67,9 @@
 	U2WE,	16,	// 0x3f - USB2 Wake Enable Bitmap
 	U3WE,	8,	// 0x41 - USB3 Wake Enable Bitmap
 	UIOR,	8,	// 0x42 - UART debug controller init on S3 resume
+	EPCS,	8,	// 0x43 - SGX Enabled status
+	EMNA,	64,	// 0x44 - 0x4B EPC base address
+	ELNG,	64,	// 0x4C - 0x53 EPC Length
 
 	/* ChromeOS specific */
 	Offset (0x100),
diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index 03c2570..e40dd6b 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -72,3 +72,8 @@
 		Return (Arg3)
 	}
 }
+
+/* SGX */
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)
+#include <soc/intel/common/acpi/sgx.asl>
+#endif
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 8272336..498bb2b 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -58,6 +58,9 @@
 	u16	u2we; /* 0x3f - USB2 Wake Enable Bitmap */
 	u8	u3we; /* 0x41 - USB3 Wake Enable Bitmap */
 	u8	uior; /* 0x42 - UART debug controller init on S3 resume */
+	u8	ecps; /* 0x43 - SGX Enabled status */
+	u64	emna; /* 0x44 - 0x4B EPC base address */
+	u64	elng; /* 0x4C - 0x53 EPC Length */
 	u8	unused[189];
 
 	/* ChromeOS specific (0x100 - 0xfff) */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie95eb79a01e1c0005e0f137b015b7fe000c1ab2a
Gerrit-Change-Number: 21971
Gerrit-PatchSet: 1
Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
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