<p>Pratikkumar V Prajapati has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21971">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Add GNVS variables and include SGX ASL<br><br>- add GNVS variables for SGX<br>- include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set<br><br>Change-Id: Ie95eb79a01e1c0005e0f137b015b7fe000c1ab2a<br>Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com><br>---<br>M src/soc/intel/skylake/acpi/globalnvs.asl<br>M src/soc/intel/skylake/acpi/pch.asl<br>M src/soc/intel/skylake/include/soc/nvs.h<br>3 files changed, 11 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/21971/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl<br>index 8a7606c..5564f02 100644<br>--- a/src/soc/intel/skylake/acpi/globalnvs.asl<br>+++ b/src/soc/intel/skylake/acpi/globalnvs.asl<br>@@ -67,6 +67,9 @@<br>     U2WE,   16,     // 0x3f - USB2 Wake Enable Bitmap<br>     U3WE,   8,      // 0x41 - USB3 Wake Enable Bitmap<br>     UIOR,   8,      // 0x42 - UART debug controller init on S3 resume<br>+    EPCS,   8,      // 0x43 - SGX Enabled status<br>+ EMNA,   64,     // 0x44 - 0x4B EPC base address<br>+      ELNG,   64,     // 0x4C - 0x53 EPC Length<br> <br>  /* ChromeOS specific */<br>       Offset (0x100),<br>diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl<br>index 03c2570..e40dd6b 100644<br>--- a/src/soc/intel/skylake/acpi/pch.asl<br>+++ b/src/soc/intel/skylake/acpi/pch.asl<br>@@ -72,3 +72,8 @@<br>           Return (Arg3)<br>         }<br> }<br>+<br>+/* SGX */<br>+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)<br>+#include <soc/intel/common/acpi/sgx.asl><br>+#endif<br>diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h<br>index 8272336..498bb2b 100644<br>--- a/src/soc/intel/skylake/include/soc/nvs.h<br>+++ b/src/soc/intel/skylake/include/soc/nvs.h<br>@@ -58,6 +58,9 @@<br>    u16     u2we; /* 0x3f - USB2 Wake Enable Bitmap */<br>    u8      u3we; /* 0x41 - USB3 Wake Enable Bitmap */<br>    u8      uior; /* 0x42 - UART debug controller init on S3 resume */<br>+   u8      ecps; /* 0x43 - SGX Enabled status */<br>+        u64     emna; /* 0x44 - 0x4B EPC base address */<br>+     u64     elng; /* 0x4C - 0x53 EPC Length */<br>    u8      unused[189];<br> <br>       /* ChromeOS specific (0x100 - 0xfff) */<br></pre><p>To view, visit <a href="https://review.coreboot.org/21971">change 21971</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21971"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie95eb79a01e1c0005e0f137b015b7fe000c1ab2a </div>
<div style="display:none"> Gerrit-Change-Number: 21971 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>