[coreboot-gerrit] Change in coreboot[master]: intel/common/acpi: Add common SGX ASL

[Pratikkumar V Prajapati (Code Review)]

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21964


Change subject: intel/common/acpi: Add common SGX ASL
......................................................................

intel/common/acpi: Add common SGX ASL

- Add EPC device for SGX
- Hid is INT0E0C
- version of the object is 1.0, so _STR is "Enclave Page Cache 1.0"

Change-Id: I9efba46469a125ea99241b04fe1ae550d6e03598
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati at intel.com>
---
A src/soc/intel/common/acpi/sgx.asl
1 file changed, 73 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21964/1

diff --git a/src/soc/intel/common/acpi/sgx.asl b/src/soc/intel/common/acpi/sgx.asl
new file mode 100644
index 0000000..37c0638
--- /dev/null
+++ b/src/soc/intel/common/acpi/sgx.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+External(\_SB.EPCS, IntObj)
+External(\_SB.EMNA, IntObj)
+External(\_SB.ELNG, IntObj)
+
+Scope(\_SB)
+{
+	// Secure Enclave memory
+	Device (EPC)
+	{
+		Name (_HID, EISAID ("INT0E0C"))
+		Name (_STR, Unicode ("Enclave Page Cache 1.0"))
+		Name (_MLS, Package () {
+			Package (2) { "en", Unicode ("Enclave Page Cache 1.0") }
+		})
+
+		Name (RBUF, ResourceTemplate ()
+		{
+			// _MIN, _MAX and  _LEN get patched runtime
+			QWordMemory (
+			ResourceConsumer, // ResourceUsage
+			PosDecode,	  // Decode		_DEC
+			MinNotFixed,	  // IsMinFixed		_MIF
+			MaxNotFixed,	  // IsMaxFixed		_MAF
+			NonCacheable,	  // Cacheable		_MEM
+			ReadWrite,	  // ReadAndWrite	_RW
+			0,		  // AddressGranularity	_GRA
+			0,		  // AddressMinimum	_MIN
+			0,		  // AddressMaximum	_MAX
+			0,		  // AddressTranslation	_TRA
+			1,		  // RangeLength	_LEN
+			,		  // ResourceSourceIndex
+			,		  // ResourceSource
+			BAR0		  // DescriptorName
+			)
+		})
+
+		Method (_CRS, 0x0, NotSerialized)
+		{
+			CreateQwordField (RBUF, ^BAR0._MIN, EMIN)
+			CreateQwordField (RBUF, ^BAR0._MAX, EMAX)
+			CreateQwordField (RBUF, ^BAR0._LEN, ELEN)
+			Store (\_SB.EMNA, EMIN)
+			Store (\_SB.ELNG, ELEN)
+			Subtract (Add (\_SB.EMNA, \_SB.ELNG), 1, EMAX)
+			Return (RBUF)
+		}
+
+		Method (_STA, 0x0, NotSerialized)
+		{
+			If (LNotEqual (\_SB.EPCS, 0))
+			{
+				Return (0xF)
+			}
+			Return (0x0)
+		}
+
+	} // end EPC Device
+} // End of Scope(\_SB)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9efba46469a125ea99241b04fe1ae550d6e03598
Gerrit-Change-Number: 21964
Gerrit-PatchSet: 1
Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
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