<p>Pratikkumar V Prajapati has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21964">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/common/acpi: Add common SGX ASL<br><br>- Add EPC device for SGX<br>- Hid is INT0E0C<br>- version of the object is 1.0, so _STR is "Enclave Page Cache 1.0"<br><br>Change-Id: I9efba46469a125ea99241b04fe1ae550d6e03598<br>Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com><br>---<br>A src/soc/intel/common/acpi/sgx.asl<br>1 file changed, 73 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21964/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/acpi/sgx.asl b/src/soc/intel/common/acpi/sgx.asl<br>new file mode 100644<br>index 0000000..37c0638<br>--- /dev/null<br>+++ b/src/soc/intel/common/acpi/sgx.asl<br>@@ -0,0 +1,73 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+External(\_SB.EPCS, IntObj)<br>+External(\_SB.EMNA, IntObj)<br>+External(\_SB.ELNG, IntObj)<br>+<br>+Scope(\_SB)<br>+{<br>+ // Secure Enclave memory<br>+ Device (EPC)<br>+ {<br>+ Name (_HID, EISAID ("INT0E0C"))<br>+ Name (_STR, Unicode ("Enclave Page Cache 1.0"))<br>+ Name (_MLS, Package () {<br>+ Package (2) { "en", Unicode ("Enclave Page Cache 1.0") }<br>+ })<br>+<br>+ Name (RBUF, ResourceTemplate ()<br>+ {<br>+ // _MIN, _MAX and _LEN get patched runtime<br>+ QWordMemory (<br>+ ResourceConsumer, // ResourceUsage<br>+ PosDecode, // Decode _DEC<br>+ MinNotFixed, // IsMinFixed _MIF<br>+ MaxNotFixed, // IsMaxFixed _MAF<br>+ NonCacheable, // Cacheable _MEM<br>+ ReadWrite, // ReadAndWrite _RW<br>+ 0, // AddressGranularity _GRA<br>+ 0, // AddressMinimum _MIN<br>+ 0, // AddressMaximum _MAX<br>+ 0, // AddressTranslation _TRA<br>+ 1, // RangeLength _LEN<br>+ , // ResourceSourceIndex<br>+ , // ResourceSource<br>+ BAR0 // DescriptorName<br>+ )<br>+ })<br>+<br>+ Method (_CRS, 0x0, NotSerialized)<br>+ {<br>+ CreateQwordField (RBUF, ^BAR0._MIN, EMIN)<br>+ CreateQwordField (RBUF, ^BAR0._MAX, EMAX)<br>+ CreateQwordField (RBUF, ^BAR0._LEN, ELEN)<br>+ Store (\_SB.EMNA, EMIN)<br>+ Store (\_SB.ELNG, ELEN)<br>+ Subtract (Add (\_SB.EMNA, \_SB.ELNG), 1, EMAX)<br>+ Return (RBUF)<br>+ }<br>+<br>+ Method (_STA, 0x0, NotSerialized)<br>+ {<br>+ If (LNotEqual (\_SB.EPCS, 0))<br>+ {<br>+ Return (0xF)<br>+ }<br>+ Return (0x0)<br>+ }<br>+<br>+ } // end EPC Device<br>+} // End of Scope(\_SB)<br></pre><p>To view, visit <a href="https://review.coreboot.org/21964">change 21964</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21964"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9efba46469a125ea99241b04fe1ae550d6e03598 </div>
<div style="display:none"> Gerrit-Change-Number: 21964 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>