[coreboot-gerrit] Change in coreboot[master]: intel/common/block/sgx: Add API to enumerate SGX resources and update...

[Pratikkumar V Prajapati (Code Review)]

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21966


Change subject: intel/common/block/sgx: Add API to enumerate SGX resources and update GNVS
......................................................................

intel/common/block/sgx: Add API to enumerate SGX resources and update GNVS

Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 is called
to enumerate SGX resources.

Change-Id: I62f3fd8527e27040336c52bc78768035f4b7e5a9
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati at intel.com>
---
M src/soc/intel/common/block/include/intelblocks/msr.h
M src/soc/intel/common/block/include/intelblocks/sgx.h
M src/soc/intel/common/block/sgx/sgx.c
3 files changed, 41 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/21966/1

diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 6236915..43441e5 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -130,4 +130,13 @@
 #define PRMRR_SUPPORTED	(1<<12)
 
 #define SGX_SUPPORTED	(1<<2)
+/* Intel SDM: Table 36-6.
+ * CPUID Leaf 12H, Sub-Leaf Index 2 or Higher for enumeration of
+ * SGX Resources. Same Table  mentions about return values of the CPUID */
+#define SGX_RESOURCE_ENUM_CPUID_LEAF	(0x12)
+#define SGX_RESOURCE_ENUM_CPUID_SUBLEAF	(0x2)
+#define SGX_RESOURCE_ENUM_BIT	(0x1)
+#define SGX_RESOURCE_MASK_LO	(0xfffff000UUL)
+#define SGX_RESOURCE_MASK_HI	(0xfffffUUL)
+
 #endif	/* SOC_INTEL_COMMON_MSR_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h
index f1dd891..02274eb 100644
--- a/src/soc/intel/common/block/include/intelblocks/sgx.h
+++ b/src/soc/intel/common/block/include/intelblocks/sgx.h
@@ -16,6 +16,8 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_SGX_H
 #define SOC_INTEL_COMMON_BLOCK_SGX_H
 
+#include <soc/nvs.h>
+
 struct sgx_param {
 	uint8_t enable;
 };
@@ -42,4 +44,7 @@
  * returns 0, if able to get SGX params; otherwise returns -1 */
 int soc_fill_sgx_param(struct sgx_param *sgx_param);
 
+/* Fill GNVS data with SGX status, EPC base and length */
+void sgx_fill_gnvs(struct global_nvs_t *gnvs);
+
 #endif	/* SOC_INTEL_COMMON_BLOCK_SGX_H */
diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c
index 3c3ab4d..69330b4 100644
--- a/src/soc/intel/common/block/sgx/sgx.c
+++ b/src/soc/intel/common/block/sgx/sgx.c
@@ -222,3 +222,30 @@
 	if (is_prmrr_approved())
 		activate_sgx();
 }
+
+void sgx_fill_gnvs(struct global_nvs_t *gnvs)
+{
+	struct cpuid_result cpuid_regs;
+
+	/* Get EPC base and size. */
+	cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF,
+				SGX_RESOURCE_ENUM_CPUID_SUBLEAF);
+
+	if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) {
+		/* EPC section enumerated */
+		gnvs->ecps = 1;
+		gnvs->emna = ((uint64_t) (cpuid_regs.ebx &
+						SGX_RESOURCE_MASK_HI) << 32) +
+				(uint64_t)(cpuid_regs.eax &
+						SGX_RESOURCE_MASK_LO);
+
+		gnvs->elng = ((uint64_t) (cpuid_regs.edx &
+						SGX_RESOURCE_MASK_HI) << 32) +
+				(uint64_t)(cpuid_regs.ecx &
+						SGX_RESOURCE_MASK_LO);
+	}
+
+	printk(BIOS_DEBUG,
+		"SGX: gnvs ECP status = %d base = 0x%llx len = 0x%llx\n",
+			gnvs->ecps, gnvs->emna, gnvs->elng);
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I62f3fd8527e27040336c52bc78768035f4b7e5a9
Gerrit-Change-Number: 21966
Gerrit-PatchSet: 1
Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
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