<p>Pratikkumar V Prajapati has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21966">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/common/block/sgx: Add API to enumerate SGX resources and update GNVS<br><br>Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 is called<br>to enumerate SGX resources.<br><br>Change-Id: I62f3fd8527e27040336c52bc78768035f4b7e5a9<br>Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com><br>---<br>M src/soc/intel/common/block/include/intelblocks/msr.h<br>M src/soc/intel/common/block/include/intelblocks/sgx.h<br>M src/soc/intel/common/block/sgx/sgx.c<br>3 files changed, 41 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/21966/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h<br>index 6236915..43441e5 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/msr.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/msr.h<br>@@ -130,4 +130,13 @@<br> #define PRMRR_SUPPORTED   (1<<12)<br> <br> #define SGX_SUPPORTED        (1<<2)<br>+/* Intel SDM: Table 36-6.<br>+ * CPUID Leaf 12H, Sub-Leaf Index 2 or Higher for enumeration of<br>+ * SGX Resources. Same Table  mentions about return values of the CPUID */<br>+#define SGX_RESOURCE_ENUM_CPUID_LEAF (0x12)<br>+#define SGX_RESOURCE_ENUM_CPUID_SUBLEAF        (0x2)<br>+#define SGX_RESOURCE_ENUM_BIT   (0x1)<br>+#define SGX_RESOURCE_MASK_LO    (0xfffff000UUL)<br>+#define SGX_RESOURCE_MASK_HI  (0xfffffUUL)<br>+<br> #endif        /* SOC_INTEL_COMMON_MSR_H */<br>diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h<br>index f1dd891..02274eb 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/sgx.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/sgx.h<br>@@ -16,6 +16,8 @@<br> #ifndef SOC_INTEL_COMMON_BLOCK_SGX_H<br> #define SOC_INTEL_COMMON_BLOCK_SGX_H<br> <br>+#include <soc/nvs.h><br>+<br> struct sgx_param {<br>        uint8_t enable;<br> };<br>@@ -42,4 +44,7 @@<br>  * returns 0, if able to get SGX params; otherwise returns -1 */<br> int soc_fill_sgx_param(struct sgx_param *sgx_param);<br> <br>+/* Fill GNVS data with SGX status, EPC base and length */<br>+void sgx_fill_gnvs(struct global_nvs_t *gnvs);<br>+<br> #endif   /* SOC_INTEL_COMMON_BLOCK_SGX_H */<br>diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c<br>index 3c3ab4d..69330b4 100644<br>--- a/src/soc/intel/common/block/sgx/sgx.c<br>+++ b/src/soc/intel/common/block/sgx/sgx.c<br>@@ -222,3 +222,30 @@<br>     if (is_prmrr_approved())<br>              activate_sgx();<br> }<br>+<br>+void sgx_fill_gnvs(struct global_nvs_t *gnvs)<br>+{<br>+   struct cpuid_result cpuid_regs;<br>+<br>+   /* Get EPC base and size. */<br>+ cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF,<br>+                         SGX_RESOURCE_ENUM_CPUID_SUBLEAF);<br>+<br>+ if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) {<br>+            /* EPC section enumerated */<br>+         gnvs->ecps = 1;<br>+           gnvs->emna = ((uint64_t) (cpuid_regs.ebx &<br>+                                            SGX_RESOURCE_MASK_HI) << 32) +<br>+                         (uint64_t)(cpuid_regs.eax &<br>+                                              SGX_RESOURCE_MASK_LO);<br>+<br>+            gnvs->elng = ((uint64_t) (cpuid_regs.edx &<br>+                                            SGX_RESOURCE_MASK_HI) << 32) +<br>+                         (uint64_t)(cpuid_regs.ecx &<br>+                                              SGX_RESOURCE_MASK_LO);<br>+       }<br>+<br>+ printk(BIOS_DEBUG,<br>+           "SGX: gnvs ECP status = %d base = 0x%llx len = 0x%llx\n",<br>+                  gnvs->ecps, gnvs->emna, gnvs->elng);<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21966">change 21966</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21966"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I62f3fd8527e27040336c52bc78768035f4b7e5a9 </div>
<div style="display:none"> Gerrit-Change-Number: 21966 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>