[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Set platform Debug Probe Type

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21942


Change subject: soc/intel/cannonlake: Set platform Debug Probe Type
......................................................................

soc/intel/cannonlake: Set platform Debug Probe Type

Add option for user to select what kind of probe can be used for
platform debug.

TEST=Select to XDP and boot up system with XDP hooked, able to halt.

Change-Id: Ib6add93e3f1c8a646aa625a4cea9be0acecc0487
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/romstage.c
2 files changed, 7 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/21942/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index ee908f0..cf7b8c1 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -206,6 +206,11 @@
 	 */
 	uint32_t PrmrrSize;
 	uint8_t PmTimerDisabled;
+	/* Descired platform debug type.
+	 * 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
+	 * 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC)
+	 */
+	uint8_t DebugConsent;
 	/*
 	 * SerialIO device mode selection:
 	 *
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 3c26ec2..296f4f8 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -105,6 +105,8 @@
 
 	/* Enable SMBus controller based on config */
 	m_cfg->SmbusEnable = config->SmbusEnable;
+	/* Set Debug probe type */
+	m_cfg->PlatformDebugConsent = config->DebugConsent;
 
 	mainboard_memory_init_params(mupd);
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib6add93e3f1c8a646aa625a4cea9be0acecc0487
Gerrit-Change-Number: 21942
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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