[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Fix HECI error on reset

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21930


Change subject: soc/intel/cannonlake: Fix HECI error on reset
......................................................................

soc/intel/cannonlake: Fix HECI error on reset

Move HECI init from bootblock to romstage, the HECI bar saved by
CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage
will be read back from PCI.

TEST= Force global reset from FSP and read back HECI bar in debug print.

Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/include/soc/iomap.h
M src/soc/intel/cannonlake/reset.c
M src/soc/intel/cannonlake/romstage/romstage.c
4 files changed, 14 insertions(+), 8 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/21930/1

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 0062c0d..ae3fe6b 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -15,7 +15,6 @@
  */
 
 #include <device/device.h>
-#include <intelblocks/cse.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/rtc.h>
@@ -194,8 +193,6 @@
 	smbus_common_init();
 
 	enable_rtc_upper_bank();
-
-	heci_init(HECI1_BASE_ADDRESS);
 
 	clear_cbmem_top();
 }
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index add5ee8..22430f0 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -63,7 +63,7 @@
 
 #define GPIO_BASE_SIZE		0x10000
 
-#define HECI1_BASE_ADDRESS		0xFEDA2000
+#define HECI1_BASE_ADDRESS	0xfeda2000
 
 /* PTT registers */
 #define PTT_TXT_BASE_ADDRESS	0xfed30800
diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c
index ca82bd6..5eb692e 100644
--- a/src/soc/intel/cannonlake/reset.c
+++ b/src/soc/intel/cannonlake/reset.c
@@ -16,10 +16,12 @@
 #include <compiler.h>
 #include <console/console.h>
 #include <intelblocks/cse.h>
+#include <intelblocks/pmclib.h>
 #include <fsp/util.h>
 #include <reset.h>
 #include <string.h>
 #include <timer.h>
+#include <soc/pci_devs.h>
 
 /* Reset Request  */
 #define MKHI_GLOBAL_RESET			0x0b
@@ -33,6 +35,11 @@
 #define BIOS_HOST_ADD				0x00
 #define HECI_MKHI_ADD				0x07
 
+static int cnl_global_reset(void)
+{
+	pmc_global_reset_enable(1);
+	hard_reset();
+}
 static int send_heci_reset_message(void)
 {
 	int status;
@@ -82,10 +89,8 @@
 {
 	/* Ask CSE to do the global reset */
 	send_heci_reset_message();
-	/*
-	 * TODO: Presumbily we shouldn't return. But if we did, fallback to
-	 * alternative way of triggered global reset provided by pmclib.
-	 */
+	/* global reset if CSE fail to reset */
+	cnl_global_reset();
 }
 
 void chipset_handle_reset(uint32_t status)
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 1775cae..3c26ec2 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -21,8 +21,10 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <fsp/util.h>
+#include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
 #include <memory_info.h>
+#include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
@@ -41,6 +43,8 @@
 
 	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
 	systemagent_early_init();
+	/* initialize Heci interface */
+	heci_init(HECI1_BASE_ADDRESS);
 
 	timestamp_add_now(TS_START_ROMSTAGE);
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b
Gerrit-Change-Number: 21930
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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