<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21930">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Fix HECI error on reset<br><br>Move HECI init from bootblock to romstage, the HECI bar saved by<br>CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage<br>will be read back from PCI.<br><br>TEST= Force global reset from FSP and read back HECI bar in debug print.<br><br>Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/bootblock/pch.c<br>M src/soc/intel/cannonlake/include/soc/iomap.h<br>M src/soc/intel/cannonlake/reset.c<br>M src/soc/intel/cannonlake/romstage/romstage.c<br>4 files changed, 14 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/21930/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c<br>index 0062c0d..ae3fe6b 100644<br>--- a/src/soc/intel/cannonlake/bootblock/pch.c<br>+++ b/src/soc/intel/cannonlake/bootblock/pch.c<br>@@ -15,7 +15,6 @@<br> */<br> <br> #include <device/device.h><br>-#include <intelblocks/cse.h><br> #include <intelblocks/fast_spi.h><br> #include <intelblocks/pcr.h><br> #include <intelblocks/rtc.h><br>@@ -194,8 +193,6 @@<br> smbus_common_init();<br> <br> enable_rtc_upper_bank();<br>-<br>- heci_init(HECI1_BASE_ADDRESS);<br> <br> clear_cbmem_top();<br> }<br>diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h<br>index add5ee8..22430f0 100644<br>--- a/src/soc/intel/cannonlake/include/soc/iomap.h<br>+++ b/src/soc/intel/cannonlake/include/soc/iomap.h<br>@@ -63,7 +63,7 @@<br> <br> #define GPIO_BASE_SIZE 0x10000<br> <br>-#define HECI1_BASE_ADDRESS 0xFEDA2000<br>+#define HECI1_BASE_ADDRESS 0xfeda2000<br> <br> /* PTT registers */<br> #define PTT_TXT_BASE_ADDRESS 0xfed30800<br>diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c<br>index ca82bd6..5eb692e 100644<br>--- a/src/soc/intel/cannonlake/reset.c<br>+++ b/src/soc/intel/cannonlake/reset.c<br>@@ -16,10 +16,12 @@<br> #include <compiler.h><br> #include <console/console.h><br> #include <intelblocks/cse.h><br>+#include <intelblocks/pmclib.h><br> #include <fsp/util.h><br> #include <reset.h><br> #include <string.h><br> #include <timer.h><br>+#include <soc/pci_devs.h><br> <br> /* Reset Request */<br> #define MKHI_GLOBAL_RESET 0x0b<br>@@ -33,6 +35,11 @@<br> #define BIOS_HOST_ADD 0x00<br> #define HECI_MKHI_ADD 0x07<br> <br>+static int cnl_global_reset(void)<br>+{<br>+ pmc_global_reset_enable(1);<br>+ hard_reset();<br>+}<br> static int send_heci_reset_message(void)<br> {<br> int status;<br>@@ -82,10 +89,8 @@<br> {<br> /* Ask CSE to do the global reset */<br> send_heci_reset_message();<br>- /*<br>- * TODO: Presumbily we shouldn't return. But if we did, fallback to<br>- * alternative way of triggered global reset provided by pmclib.<br>- */<br>+ /* global reset if CSE fail to reset */<br>+ cnl_global_reset();<br> }<br> <br> void chipset_handle_reset(uint32_t status)<br>diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c<br>index 1775cae..3c26ec2 100644<br>--- a/src/soc/intel/cannonlake/romstage/romstage.c<br>+++ b/src/soc/intel/cannonlake/romstage/romstage.c<br>@@ -21,8 +21,10 @@<br> #include <cbmem.h><br> #include <console/console.h><br> #include <fsp/util.h><br>+#include <intelblocks/cse.h><br> #include <intelblocks/pmclib.h><br> #include <memory_info.h><br>+#include <soc/iomap.h><br> #include <soc/pci_devs.h><br> #include <soc/pm.h><br> #include <soc/romstage.h><br>@@ -41,6 +43,8 @@<br> <br> /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */<br> systemagent_early_init();<br>+ /* initialize Heci interface */<br>+ heci_init(HECI1_BASE_ADDRESS);<br> <br> timestamp_add_now(TS_START_ROMSTAGE);<br> s3wake = pmc_fill_power_state(ps) == ACPI_S3;<br></pre><p>To view, visit <a href="https://review.coreboot.org/21930">change 21930</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21930"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b </div>
<div style="display:none"> Gerrit-Change-Number: 21930 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>