[coreboot-gerrit] Change in coreboot[master]: [WIP] nb/via/cn700: Split tolmk calculation out of pci_domain_set_res...
Jonathan Neuschäfer (Code Review)
gerrit at coreboot.org
Thu Oct 5 12:49:59 CEST 2017
Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21893
Change subject: [WIP] nb/via/cn700: Split tolmk calculation out of pci_domain_set_resources
......................................................................
[WIP] nb/via/cn700: Split tolmk calculation out of pci_domain_set_resources
Change-Id: I6892027db70ad5d5a7c8a9865041a656bca74a03
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/northbridge/via/cn700/Makefile.inc
M src/northbridge/via/cn700/northbridge.c
A src/northbridge/via/cn700/ram_calc.c
A src/northbridge/via/cn700/ram_calc.h
4 files changed, 98 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/21893/1
diff --git a/src/northbridge/via/cn700/Makefile.inc b/src/northbridge/via/cn700/Makefile.inc
index f7f288f..977460b 100644
--- a/src/northbridge/via/cn700/Makefile.inc
+++ b/src/northbridge/via/cn700/Makefile.inc
@@ -19,6 +19,7 @@
ramstage-y += northbridge.c
ramstage-y += agp.c
ramstage-y += vga.c
+ramstage-y += ram_calc.c
romstage-y += raminit.c
endif
diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c
index 2121162..1ea4e51 100644
--- a/src/northbridge/via/cn700/northbridge.c
+++ b/src/northbridge/via/cn700/northbridge.c
@@ -29,6 +29,7 @@
#include <cpu/cpu.h>
#include "northbridge.h"
#include "cn700.h"
+#include "ram_calc.h"
static void memctrl_init(device_t dev)
{
@@ -95,51 +96,23 @@
static void pci_domain_set_resources(device_t dev)
{
- /* The order is important to find the correct RAM size. */
- static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
- device_t mc_dev;
- u32 pci_tolm;
+ unsigned long tolmk;
+ int idx;
printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n");
- pci_tolm = find_pci_tolm(dev->link_list);
- mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
+ tolmk = cn700_get_tolmk(dev);
- if (mc_dev) {
- unsigned long tomk, tolmk;
- unsigned char rambits;
- int i, idx;
+ set_late_cbmem_top((tolmk - CONFIG_VIDEO_MB * 1024) * 1024);
- /*
- * Once the register value is not zero, the RAM size is
- * this register's value multiply 64 * 1024 * 1024.
- */
- for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
- rambits = pci_read_config8(mc_dev, ramregs[i]);
- if (rambits != 0)
- break;
- }
+ /* Report the memory regions. */
+ idx = 10;
+ /* TODO: Hole needed? */
+ ram_resource(dev, idx++, 0, 640); /* First 640k */
+ /* Leave a hole for VGA, 0xa0000 - 0xc0000 */
+ ram_resource(dev, idx++, 768,
+ (tolmk - 768 - CONFIG_VIDEO_MB * 1024));
- tomk = rambits * 64 * 1024;
- printk(BIOS_DEBUG, "tomk is 0x%lx\n", tomk);
- /* Compute the Top Of Low Memory (TOLM), in Kb. */
- tolmk = pci_tolm >> 10;
- if (tolmk >= tomk) {
- /* The PCI hole does does not overlap the memory. */
- tolmk = tomk;
- }
-
- set_late_cbmem_top((tolmk - CONFIG_VIDEO_MB * 1024) * 1024);
-
- /* Report the memory regions. */
- idx = 10;
- /* TODO: Hole needed? */
- ram_resource(dev, idx++, 0, 640); /* First 640k */
- /* Leave a hole for VGA, 0xa0000 - 0xc0000 */
- ram_resource(dev, idx++, 768,
- (tolmk - 768 - CONFIG_VIDEO_MB * 1024));
- }
assign_resources(dev->link_list);
}
diff --git a/src/northbridge/via/cn700/ram_calc.c b/src/northbridge/via/cn700/ram_calc.c
new file mode 100644
index 0000000..3686bf4
--- /dev/null
+++ b/src/northbridge/via/cn700/ram_calc.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#include "cn700.h"
+#include "ram_calc.h"
+
+/* Get the top of low memory in KiB. */
+unsigned long cn700_get_tolmk(device_t dev)
+{
+ /* The order is important to find the correct RAM size. */
+ static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
+ unsigned long tomk, tolmk;
+ unsigned char rambits;
+ int i;
+ device_t mc_dev;
+ u32 pci_tolm;
+
+ pci_tolm = find_pci_tolm(dev->link_list);
+ mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
+
+ if (!mc_dev)
+ die("Error: Memory controller device not found!\n");
+
+ /*
+ * Once the register value is not zero, the RAM size is
+ * this register's value multiply 64 * 1024 * 1024.
+ */
+ for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
+ rambits = pci_read_config8(mc_dev, ramregs[i]);
+ if (rambits != 0)
+ break;
+ }
+
+ tomk = rambits * 64 * 1024;
+ printk(BIOS_DEBUG, "tomk is 0x%lx\n", tomk);
+ /* Compute the Top Of Low Memory (TOLM), in Kb. */
+ tolmk = pci_tolm >> 10;
+ if (tolmk >= tomk) {
+ /* The PCI hole does does not overlap the memory. */
+ tolmk = tomk;
+ }
+
+ return tolmk;
+}
diff --git a/src/northbridge/via/cn700/ram_calc.h b/src/northbridge/via/cn700/ram_calc.h
new file mode 100644
index 0000000..f467a69
--- /dev/null
+++ b/src/northbridge/via/cn700/ram_calc.h
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Get the top of low memory in KiB. */
+extern unsigned long cn700_get_tolmk(device_t dev);
--
To view, visit https://review.coreboot.org/21893
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6892027db70ad5d5a7c8a9865041a656bca74a03
Gerrit-Change-Number: 21893
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
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