<p>Jonathan Neuschäfer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21893">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP] nb/via/cn700: Split tolmk calculation out of pci_domain_set_resources<br><br>Change-Id: I6892027db70ad5d5a7c8a9865041a656bca74a03<br>Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net><br>---<br>M src/northbridge/via/cn700/Makefile.inc<br>M src/northbridge/via/cn700/northbridge.c<br>A src/northbridge/via/cn700/ram_calc.c<br>A src/northbridge/via/cn700/ram_calc.h<br>4 files changed, 98 insertions(+), 39 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/21893/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/via/cn700/Makefile.inc b/src/northbridge/via/cn700/Makefile.inc<br>index f7f288f..977460b 100644<br>--- a/src/northbridge/via/cn700/Makefile.inc<br>+++ b/src/northbridge/via/cn700/Makefile.inc<br>@@ -19,6 +19,7 @@<br> ramstage-y += northbridge.c<br> ramstage-y += agp.c<br> ramstage-y += vga.c<br>+ramstage-y += ram_calc.c<br> romstage-y += raminit.c<br> <br> endif<br>diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c<br>index 2121162..1ea4e51 100644<br>--- a/src/northbridge/via/cn700/northbridge.c<br>+++ b/src/northbridge/via/cn700/northbridge.c<br>@@ -29,6 +29,7 @@<br> #include <cpu/cpu.h><br> #include "northbridge.h"<br> #include "cn700.h"<br>+#include "ram_calc.h"<br> <br> static void memctrl_init(device_t dev)<br> {<br>@@ -95,51 +96,23 @@<br> <br> static void pci_domain_set_resources(device_t dev)<br> {<br>- /* The order is important to find the correct RAM size. */<br>- static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };<br>- device_t mc_dev;<br>- u32 pci_tolm;<br>+ unsigned long tolmk;<br>+ int idx;<br> <br> printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n");<br> <br>- pci_tolm = find_pci_tolm(dev->link_list);<br>- mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,<br>- PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);<br>+ tolmk = cn700_get_tolmk(dev);<br> <br>- if (mc_dev) {<br>- unsigned long tomk, tolmk;<br>- unsigned char rambits;<br>- int i, idx;<br>+ set_late_cbmem_top((tolmk - CONFIG_VIDEO_MB * 1024) * 1024);<br> <br>- /*<br>- * Once the register value is not zero, the RAM size is<br>- * this register's value multiply 64 * 1024 * 1024.<br>- */<br>- for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {<br>- rambits = pci_read_config8(mc_dev, ramregs[i]);<br>- if (rambits != 0)<br>- break;<br>- }<br>+ /* Report the memory regions. */<br>+ idx = 10;<br>+ /* TODO: Hole needed? */<br>+ ram_resource(dev, idx++, 0, 640); /* First 640k */<br>+ /* Leave a hole for VGA, 0xa0000 - 0xc0000 */<br>+ ram_resource(dev, idx++, 768,<br>+ (tolmk - 768 - CONFIG_VIDEO_MB * 1024));<br> <br>- tomk = rambits * 64 * 1024;<br>- printk(BIOS_DEBUG, "tomk is 0x%lx\n", tomk);<br>- /* Compute the Top Of Low Memory (TOLM), in Kb. */<br>- tolmk = pci_tolm >> 10;<br>- if (tolmk >= tomk) {<br>- /* The PCI hole does does not overlap the memory. */<br>- tolmk = tomk;<br>- }<br>-<br>- set_late_cbmem_top((tolmk - CONFIG_VIDEO_MB * 1024) * 1024);<br>-<br>- /* Report the memory regions. */<br>- idx = 10;<br>- /* TODO: Hole needed? */<br>- ram_resource(dev, idx++, 0, 640); /* First 640k */<br>- /* Leave a hole for VGA, 0xa0000 - 0xc0000 */<br>- ram_resource(dev, idx++, 768,<br>- (tolmk - 768 - CONFIG_VIDEO_MB * 1024));<br>- }<br> assign_resources(dev->link_list);<br> }<br> <br>diff --git a/src/northbridge/via/cn700/ram_calc.c b/src/northbridge/via/cn700/ram_calc.c<br>new file mode 100644<br>index 0000000..3686bf4<br>--- /dev/null<br>+++ b/src/northbridge/via/cn700/ram_calc.c<br>@@ -0,0 +1,65 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2008 VIA Technologies, Inc.<br>+ * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)<br>+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <device/pci_ids.h><br>+<br>+#include "cn700.h"<br>+#include "ram_calc.h"<br>+<br>+/* Get the top of low memory in KiB. */<br>+unsigned long cn700_get_tolmk(device_t dev)<br>+{<br>+ /* The order is important to find the correct RAM size. */<br>+ static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };<br>+ unsigned long tomk, tolmk;<br>+ unsigned char rambits;<br>+ int i;<br>+ device_t mc_dev;<br>+ u32 pci_tolm;<br>+<br>+ pci_tolm = find_pci_tolm(dev->link_list);<br>+ mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,<br>+ PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);<br>+<br>+ if (!mc_dev)<br>+ die("Error: Memory controller device not found!\n");<br>+<br>+ /*<br>+ * Once the register value is not zero, the RAM size is<br>+ * this register's value multiply 64 * 1024 * 1024.<br>+ */<br>+ for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {<br>+ rambits = pci_read_config8(mc_dev, ramregs[i]);<br>+ if (rambits != 0)<br>+ break;<br>+ }<br>+<br>+ tomk = rambits * 64 * 1024;<br>+ printk(BIOS_DEBUG, "tomk is 0x%lx\n", tomk);<br>+ /* Compute the Top Of Low Memory (TOLM), in Kb. */<br>+ tolmk = pci_tolm >> 10;<br>+ if (tolmk >= tomk) {<br>+ /* The PCI hole does does not overlap the memory. */<br>+ tolmk = tomk;<br>+ }<br>+<br>+ return tolmk;<br>+}<br>diff --git a/src/northbridge/via/cn700/ram_calc.h b/src/northbridge/via/cn700/ram_calc.h<br>new file mode 100644<br>index 0000000..f467a69<br>--- /dev/null<br>+++ b/src/northbridge/via/cn700/ram_calc.h<br>@@ -0,0 +1,20 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2008 VIA Technologies, Inc.<br>+ * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)<br>+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* Get the top of low memory in KiB. */<br>+extern unsigned long cn700_get_tolmk(device_t dev);<br></pre><p>To view, visit <a href="https://review.coreboot.org/21893">change 21893</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21893"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6892027db70ad5d5a7c8a9865041a656bca74a03 </div>
<div style="display:none"> Gerrit-Change-Number: 21893 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>