[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Enabled MRC Cache

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21892


Change subject: soc/intel/cannonlake: Enabled MRC Cache
......................................................................

soc/intel/cannonlake: Enabled MRC Cache

Enable MRC cache by default.

TEST=Warm reset and check coreboot serial log.

Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
1 file changed, 2 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/21892/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 2d9ffa4..756cdc4 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -15,6 +15,7 @@
 	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select C_ENVIRONMENT_BOOTBLOCK
+	select CACHE_MRC_SETTINGS
 	select COMMON_FADT
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select GENERIC_GPIO_LIB
@@ -26,6 +27,7 @@
 	select INTEL_CAR_NEM_ENHANCED
 	select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
 	select IOAPIC
+	select MRC_SETTINGS_PROTECT
 	select PARALLEL_MP
 	select PARALLEL_MP_AP_WORK
 	select PLATFORM_USES_FSP2_0

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e
Gerrit-Change-Number: 21892
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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