[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Enable bus master for sata

[Kane Chen (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/21890

to look at the new patch set (#3).

Change subject: soc/intel/skylake: Enable bus master for sata
......................................................................

soc/intel/skylake: Enable bus master for sata

The bus master needs to be enabled so that
the busy bit in ahci PORT_TFDATA will be clear
by controller when depthcharge tries to wait
for sata to complete spin-up during ahci init.

Otherwise, the timeout will happen and cause
5 seconds delay in depthcharge.

BUG=b:37639063
BRANCH=none
TEST=verify that the sata timeout is gone in
     depthcharge

Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8
Signed-off-by: Kane Chen <kane.chen at intel.com>
---
M src/soc/intel/common/block/sata/sata.c
1 file changed, 5 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/21890/3
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8
Gerrit-Change-Number: 21890
Gerrit-PatchSet: 3
Gerrit-Owner: Kane Chen <kane.chen at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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