<p>Kane Chen <strong>uploaded patch set #3</strong> to this change.</p><p><a href="https://review.coreboot.org/21890">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Enable bus master for sata<br><br>The bus master needs to be enabled so that<br>the busy bit in ahci PORT_TFDATA will be clear<br>by controller when depthcharge tries to wait<br>for sata to complete spin-up during ahci init.<br><br>Otherwise, the timeout will happen and cause<br>5 seconds delay in depthcharge.<br><br>BUG=b:37639063<br>BRANCH=none<br>TEST=verify that the sata timeout is gone in<br>     depthcharge<br><br>Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8<br>Signed-off-by: Kane Chen <kane.chen@intel.com><br>---<br>M src/soc/intel/common/block/sata/sata.c<br>1 file changed, 5 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/21890/3</pre><p>To view, visit <a href="https://review.coreboot.org/21890">change 21890</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21890"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newpatchset </div>
<div style="display:none"> Gerrit-Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 </div>
<div style="display:none"> Gerrit-Change-Number: 21890 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Kane Chen <kane.chen@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>