[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Enable bus master for sata

[Kane Chen (Code Review)]

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/21890


Change subject: soc/intel/skylake: Enable bus master for sata
......................................................................

soc/intel/skylake: Enable bus master for sata

The bus master needs to be enabled so that
the busy bit will be clear by controller
when depthcharge tries to wait for sata
to complete spin-up during ahci init.
Otherwise, the timeout will happen and cause
5 seconds delay in depthcharge

Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8
Signed-off-by: Kane Chen <kane.chen at intel.com>
---
M src/soc/intel/common/block/sata/sata.c
1 file changed, 5 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/21890/1

diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c
index 5cacc95..f300656 100644
--- a/src/soc/intel/common/block/sata/sata.c
+++ b/src/soc/intel/common/block/sata/sata.c
@@ -45,6 +45,11 @@
 	u32 port_impl, temp;
 
 	dev = PCH_DEV_SATA;
+
+	/* Set Bus Master */
+	temp = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER);
+
 	/* Read Ports Implemented (GHC_PI) */
 	port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED) & 0x07;
 	/* Port enable */

-- 
To view, visit https://review.coreboot.org/21890
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8
Gerrit-Change-Number: 21890
Gerrit-PatchSet: 1
Gerrit-Owner: Kane Chen <kane.chen at intel.com>
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