<p>Kane Chen has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21890">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Enable bus master for sata<br><br>The bus master needs to be enabled so that<br>the busy bit will be clear by controller<br>when depthcharge tries to wait for sata<br>to complete spin-up during ahci init.<br>Otherwise, the timeout will happen and cause<br>5 seconds delay in depthcharge<br><br>Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8<br>Signed-off-by: Kane Chen <kane.chen@intel.com><br>---<br>M src/soc/intel/common/block/sata/sata.c<br>1 file changed, 5 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/21890/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c<br>index 5cacc95..f300656 100644<br>--- a/src/soc/intel/common/block/sata/sata.c<br>+++ b/src/soc/intel/common/block/sata/sata.c<br>@@ -45,6 +45,11 @@<br>         u32 port_impl, temp;<br> <br>       dev = PCH_DEV_SATA;<br>+<br>+       /* Set Bus Master */<br>+ temp = pci_read_config32(dev, PCI_COMMAND);<br>+  pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER);<br>+<br>   /* Read Ports Implemented (GHC_PI) */<br>         port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED) & 0x07;<br>  /* Port enable */<br></pre><p>To view, visit <a href="https://review.coreboot.org/21890">change 21890</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21890"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 </div>
<div style="display:none"> Gerrit-Change-Number: 21890 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kane Chen <kane.chen@intel.com> </div>