[coreboot-gerrit] Change in coreboot[master]: google/kahlee: Add defines in OemCustomize.c

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21853


Change subject: google/kahlee: Add defines in OemCustomize.c
......................................................................

google/kahlee: Add defines in OemCustomize.c

Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max
supported for the device.  AGESA's DRAM procedures follow the BKDG and
may vary depending on the number of slots on the motherboard.  DIMM
numbering and ordering is also affected by this value.

Replace hardcoded integers with defined values for DIMM slots and
number of channels.

Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/mainboard/google/kahlee/OemCustomize.c
1 file changed, 8 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/21853/1

diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index 528c7b3..878e2b9 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,16 +13,20 @@
  * GNU General Public License for more details.
  */
 
+#include <chip.h>
 #include <AGESA.h>
 #include <agesawrapper.h>
 #include <PlatformMemoryConfiguration.h>
 
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
+#define MB_DIMM_SLOTS 1
+#if MB_DIMM_SLOTS > MAX_DIMMS_PER_CH
+#error "Too many DIMM sockets defined for the mainboard"
+#endif
 
 static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
 	DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
+	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, MB_DIMM_SLOTS),
+	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
 	MOTHER_BOARD_LAYERS(LAYERS_6),
 	MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
 				0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395
Gerrit-Change-Number: 21853
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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