[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Add NV storage to ramtop

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22651


Change subject: amd/stoneyridge: Add NV storage to ramtop
......................................................................

amd/stoneyridge: Add NV storage to ramtop

The scratch registers in northbridge used for storing the top of
cacheable memory are volatile.  Add a mechanism to save and retrieve
the value from the BiosRam storage in the FCH.  These values remain
valid until RSMRST# is asserted or S5 power is lost.  The accesses to
the FCH are substantially slower than the northbridge, however, so
continue using the volatile copy when determining cbmem_top.

Change-Id: I3818cbd055ac834a79c81e2d6d58e8e268006f2e
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/Makefile.inc
M src/soc/amd/stoneyridge/ramtop.c
2 files changed, 16 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/22651/1

diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 24994d4..f5a8826 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -43,6 +43,7 @@
 bootblock-y += early_setup.c
 bootblock-y += pmutil.c
 bootblock-y += tsc_freq.c
+bootblock-y += sb_util.c
 
 romstage-y += BiosCallOuts.c
 romstage-y += romstage.c
@@ -66,6 +67,7 @@
 
 postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
 postcar-y += ramtop.c
+postcar-y += sb_util.c
 
 ramstage-y += BiosCallOuts.c
 ramstage-y += chip.c
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index 8268477..5681691 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -22,20 +22,32 @@
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>
 #include <soc/northbridge.h>
+#include <soc/southbridge.h>
 
 #define CBMEM_TOP_SCRATCHPAD 0x78
+#define CBMEM_TOP_BIOSRAM 0xf0
 
 void backup_top_of_low_cacheable(uintptr_t ramtop)
 {
+	/* save a volatile copy */
 	uint16_t top_cache = ramtop >> 16;
 	pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache);
+
+	/* and a much slower to access NV copy */
+	biosram_write32(CBMEM_TOP_BIOSRAM, ramtop);
 }
 
 uintptr_t restore_top_of_low_cacheable(void)
 {
-	uint16_t top_cache;
+	uintptr_t top_cache;
 	top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD);
-	return (top_cache << 16);
+	if (top_cache)
+		return (top_cache << 16);
+
+	/* top_cache == 0 means we lost our volatile copy.  Restore it now. */
+	top_cache = biosram_read32(CBMEM_TOP_BIOSRAM);
+	backup_top_of_low_cacheable(top_cache);
+	return top_cache;
 }
 
 void *cbmem_top(void)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3818cbd055ac834a79c81e2d6d58e8e268006f2e
Gerrit-Change-Number: 22651
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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