<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22651">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Add NV storage to ramtop<br><br>The scratch registers in northbridge used for storing the top of<br>cacheable memory are volatile.  Add a mechanism to save and retrieve<br>the value from the BiosRam storage in the FCH.  These values remain<br>valid until RSMRST# is asserted or S5 power is lost.  The accesses to<br>the FCH are substantially slower than the northbridge, however, so<br>continue using the volatile copy when determining cbmem_top.<br><br>Change-Id: I3818cbd055ac834a79c81e2d6d58e8e268006f2e<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/Makefile.inc<br>M src/soc/amd/stoneyridge/ramtop.c<br>2 files changed, 16 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/22651/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc<br>index 24994d4..f5a8826 100644<br>--- a/src/soc/amd/stoneyridge/Makefile.inc<br>+++ b/src/soc/amd/stoneyridge/Makefile.inc<br>@@ -43,6 +43,7 @@<br> bootblock-y += early_setup.c<br> bootblock-y += pmutil.c<br> bootblock-y += tsc_freq.c<br>+bootblock-y += sb_util.c<br> <br> romstage-y += BiosCallOuts.c<br> romstage-y += romstage.c<br>@@ -66,6 +67,7 @@<br> <br> postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c<br> postcar-y += ramtop.c<br>+postcar-y += sb_util.c<br> <br> ramstage-y += BiosCallOuts.c<br> ramstage-y += chip.c<br>diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c<br>index 8268477..5681691 100644<br>--- a/src/soc/amd/stoneyridge/ramtop.c<br>+++ b/src/soc/amd/stoneyridge/ramtop.c<br>@@ -22,20 +22,32 @@<br> #include <cpu/amd/mtrr.h><br> #include <cbmem.h><br> #include <soc/northbridge.h><br>+#include <soc/southbridge.h><br> <br> #define CBMEM_TOP_SCRATCHPAD 0x78<br>+#define CBMEM_TOP_BIOSRAM 0xf0<br> <br> void backup_top_of_low_cacheable(uintptr_t ramtop)<br> {<br>+      /* save a volatile copy */<br>    uint16_t top_cache = ramtop >> 16;<br>      pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache);<br>+<br>+      /* and a much slower to access NV copy */<br>+    biosram_write32(CBMEM_TOP_BIOSRAM, ramtop);<br> }<br> <br> uintptr_t restore_top_of_low_cacheable(void)<br> {<br>-        uint16_t top_cache;<br>+  uintptr_t top_cache;<br>  top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD);<br>- return (top_cache << 16);<br>+      if (top_cache)<br>+               return (top_cache << 16);<br>+<br>+   /* top_cache == 0 means we lost our volatile copy.  Restore it now. */<br>+       top_cache = biosram_read32(CBMEM_TOP_BIOSRAM);<br>+       backup_top_of_low_cacheable(top_cache);<br>+      return top_cache;<br> }<br> <br> void *cbmem_top(void)<br></pre><p>To view, visit <a href="https://review.coreboot.org/22651">change 22651</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22651"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3818cbd055ac834a79c81e2d6d58e8e268006f2e </div>
<div style="display:none"> Gerrit-Change-Number: 22651 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>