[coreboot-gerrit] Change in coreboot[master]: intel/bd82x6x: Add missing IRQ routes
Tobias Diedrich (Code Review)
gerrit at coreboot.org
Tue Nov 28 22:07:39 CET 2017
Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22622
Change subject: intel/bd82x6x: Add missing IRQ routes
......................................................................
intel/bd82x6x: Add missing IRQ routes
Add missing routing data for the gigabit ethernet, management engine
and secondary SATA controller devices.
The ACPI table was also inconsistent between the APIC and PIC routing
data.
At least the gigabit ethernet routing setup is likely needed for PXE
option roms in case they are not MSI capable (untested).
Tested using Linux with pci=nomsi.
Change-Id: Id14f4e2fb03e0a9149c443487665f6eb04c4d3bd
---
M src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
M src/southbridge/intel/bd82x6x/early_rcba.c
2 files changed, 31 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/22622/1
diff --git a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
index 0e6f960..999cd4b 100644
--- a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
@@ -27,7 +27,11 @@
Package() { 0x0001ffff, 0, 0, 18 },/* GFX PCIe INTC -> PIRQC (MSI) */
Package() { 0x0001ffff, 0, 0, 19 },/* GFX PCIe INTD -> PIRQD (MSI) */
/* XHCI 0:14.0 (ivy only) */
- Package() { 0x0014ffff, 0, 0, 19 },
+ Package() { 0x0014ffff, 0, 0, 19 },/* D20IP_XHCI XHCI INTA -> PIRQD (MSI) */
+ /* Management Enginge */
+ Package() { 0x0016ffff, 0, 0, 16 },/* D22IP_MEI1 MEI1 INTA -> PIRQA */
+ /* Gigabit Ethernet */
+ Package() { 0x0019ffff, 0, 0, 16 },/* D25IP_LIP GBE INTA -> PIRQA */
/* High Definition Audio 0:1b.0 */
Package() { 0x001bffff, 0, 0, 16 },/* D27IP_ZIP HDA INTA -> PIRQA (MSI) */
/* PCIe Root Ports 0:1c.x */
@@ -43,7 +47,7 @@
Package() { 0x001fffff, 0, 0, 17 }, /* D31IP_SIP SATA INTA -> PIRQB (MSI) */
Package() { 0x001fffff, 1, 0, 23 }, /* D31IP_SMIP SMBUS INTB -> PIRQH */
Package() { 0x001fffff, 2, 0, 16 }, /* D31IP_TTIP THRT INTC -> PIRQA */
- Package() { 0x001fffff, 3, 0, 18 },
+ Package() { 0x001fffff, 3, 0, 18 }, /* D31IP_SIP2 SATA2 INTD -> PIRQC (MSI) */
})
} Else {
Return (Package() {
@@ -56,6 +60,10 @@
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
/* XHCI 0:14.0 (ivy only) */
Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ /* Management Enginge */
+ Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ /* Gigabit Ethernet */
+ Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
/* High Definition Audio 0:1b.0 */
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
/* PCIe Root Ports 0:1c.x */
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c
index eeecb5f..6929bda 100644
--- a/src/southbridge/intel/bd82x6x/early_rcba.c
+++ b/src/southbridge/intel/bd82x6x/early_rcba.c
@@ -23,22 +23,26 @@
southbridge_configure_default_intmap(void)
{
/*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP SLOT1 INTA -> PIRQB
- * D28IP_P2IP SLOT2 INTB -> PIRQF
- * D28IP_P3IP SLOT3 INTC -> PIRQD
- * D28IP_P5IP SLOT5 INTC -> PIRQD
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQF
- * D31IP_SIP SATA INTA -> PIRQB (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQH
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ * GFX INTA -> PIRQA (MSI)
+ * D20IP_XHCIIP XHCI INTA -> PIRQD (MSI)
+ * D22IP_MEI1IP MEI1 INTA -> PIRQA
+ * D25IP_LIP GBE INTA -> PIRQA (MSI)
+ * D26IP_E2P EHCI2 INTA -> PIRQF
+ * D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ * D28IP_P1IP SLOT1 INTA -> PIRQB
+ * D28IP_P2IP SLOT2 INTB -> PIRQF
+ * D28IP_P3IP SLOT3 INTC -> PIRQD
+ * D28IP_P5IP SLOT5 INTC -> PIRQD
+ * D29IP_E1P EHCI1 INTA -> PIRQD
+ * D31IP_SIP SATA INTA -> PIRQB (MSI)
+ * D31IP_SIP2 SATA2 INTD -> PIRQC (MSI)
+ * D31IP_SMIP SMBUS INTB -> PIRQH
+ * D31IP_TTIP THRT INTC -> PIRQA
*
*/
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (INTD << D31IP_SIP2) |
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
RCBA32(D30IP) = (NOINT << D30IP_PIP);
RCBA32(D29IP) = (INTA << D29IP_E1P);
@@ -46,8 +50,10 @@
(INTC << D28IP_P3IP) | (INTC << D28IP_P5IP);
RCBA32(D27IP) = (INTA << D27IP_ZIP);
RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+ RCBA32(D25IP) = (INTA << D25IP_LIP);
+ RCBA32(D22IP) = (INTA << D22IP_MEI1IP) | (NOINT << D22IP_MEI2IP) |
+ (NOINT << D22IP_IDERIP) | (NOINT << D22IP_KTIP);
+ RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
/* Device interrupt route registers */
DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
@@ -57,6 +63,7 @@
DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D20IR, PIRQD, PIRQA, PIRQB, PIRQC);
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
--
To view, visit https://review.coreboot.org/22622
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id14f4e2fb03e0a9149c443487665f6eb04c4d3bd
Gerrit-Change-Number: 22622
Gerrit-PatchSet: 1
Gerrit-Owner: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
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