<p>Tobias Diedrich has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22622">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/bd82x6x: Add missing IRQ routes<br><br>Add missing routing data for the gigabit ethernet, management engine<br>and secondary SATA controller devices.<br><br>The ACPI table was also inconsistent between the APIC and PIC routing<br>data.<br><br>At least the gigabit ethernet routing setup is likely needed for PXE<br>option roms in case they are not MSI capable (untested).<br><br>Tested using Linux with pci=nomsi.<br><br>Change-Id: Id14f4e2fb03e0a9149c443487665f6eb04c4d3bd<br>---<br>M src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl<br>M src/southbridge/intel/bd82x6x/early_rcba.c<br>2 files changed, 31 insertions(+), 16 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/22622/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl<br>index 0e6f960..999cd4b 100644<br>--- a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl<br>+++ b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl<br>@@ -27,7 +27,11 @@<br> Package() { 0x0001ffff, 0, 0, 18 },/* GFX PCIe INTC -> PIRQC (MSI) */<br> Package() { 0x0001ffff, 0, 0, 19 },/* GFX PCIe INTD -> PIRQD (MSI) */<br> /* XHCI 0:14.0 (ivy only) */<br>- Package() { 0x0014ffff, 0, 0, 19 },<br>+ Package() { 0x0014ffff, 0, 0, 19 },/* D20IP_XHCI XHCI INTA -> PIRQD (MSI) */<br>+ /* Management Enginge */<br>+ Package() { 0x0016ffff, 0, 0, 16 },/* D22IP_MEI1 MEI1 INTA -> PIRQA */<br>+ /* Gigabit Ethernet */<br>+ Package() { 0x0019ffff, 0, 0, 16 },/* D25IP_LIP GBE INTA -> PIRQA */<br> /* High Definition Audio 0:1b.0 */<br> Package() { 0x001bffff, 0, 0, 16 },/* D27IP_ZIP HDA INTA -> PIRQA (MSI) */<br> /* PCIe Root Ports 0:1c.x */<br>@@ -43,7 +47,7 @@<br> Package() { 0x001fffff, 0, 0, 17 }, /* D31IP_SIP SATA INTA -> PIRQB (MSI) */<br> Package() { 0x001fffff, 1, 0, 23 }, /* D31IP_SMIP SMBUS INTB -> PIRQH */<br> Package() { 0x001fffff, 2, 0, 16 }, /* D31IP_TTIP THRT INTC -> PIRQA */<br>- Package() { 0x001fffff, 3, 0, 18 },<br>+ Package() { 0x001fffff, 3, 0, 18 }, /* D31IP_SIP2 SATA2 INTD -> PIRQC (MSI) */<br> })<br> } Else {<br> Return (Package() {<br>@@ -56,6 +60,10 @@<br> Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },<br> /* XHCI 0:14.0 (ivy only) */<br> Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },<br>+ /* Management Enginge */<br>+ Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>+ /* Gigabit Ethernet */<br>+ Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br> /* High Definition Audio 0:1b.0 */<br> Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br> /* PCIe Root Ports 0:1c.x */<br>diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c<br>index eeecb5f..6929bda 100644<br>--- a/src/southbridge/intel/bd82x6x/early_rcba.c<br>+++ b/src/southbridge/intel/bd82x6x/early_rcba.c<br>@@ -23,22 +23,26 @@<br> southbridge_configure_default_intmap(void)<br> {<br> /*<br>- * GFX INTA -> PIRQA (MSI)<br>- * D28IP_P1IP SLOT1 INTA -> PIRQB<br>- * D28IP_P2IP SLOT2 INTB -> PIRQF<br>- * D28IP_P3IP SLOT3 INTC -> PIRQD<br>- * D28IP_P5IP SLOT5 INTC -> PIRQD<br>- * D29IP_E1P EHCI1 INTA -> PIRQD<br>- * D26IP_E2P EHCI2 INTA -> PIRQF<br>- * D31IP_SIP SATA INTA -> PIRQB (MSI)<br>- * D31IP_SMIP SMBUS INTB -> PIRQH<br>- * D31IP_TTIP THRT INTC -> PIRQA<br>- * D27IP_ZIP HDA INTA -> PIRQA (MSI)<br>+ * GFX INTA -> PIRQA (MSI)<br>+ * D20IP_XHCIIP XHCI INTA -> PIRQD (MSI)<br>+ * D22IP_MEI1IP MEI1 INTA -> PIRQA<br>+ * D25IP_LIP GBE INTA -> PIRQA (MSI)<br>+ * D26IP_E2P EHCI2 INTA -> PIRQF<br>+ * D27IP_ZIP HDA INTA -> PIRQA (MSI)<br>+ * D28IP_P1IP SLOT1 INTA -> PIRQB<br>+ * D28IP_P2IP SLOT2 INTB -> PIRQF<br>+ * D28IP_P3IP SLOT3 INTC -> PIRQD<br>+ * D28IP_P5IP SLOT5 INTC -> PIRQD<br>+ * D29IP_E1P EHCI1 INTA -> PIRQD<br>+ * D31IP_SIP SATA INTA -> PIRQB (MSI)<br>+ * D31IP_SIP2 SATA2 INTD -> PIRQC (MSI)<br>+ * D31IP_SMIP SMBUS INTB -> PIRQH<br>+ * D31IP_TTIP THRT INTC -> PIRQA<br> *<br> <br> */<br> <br>- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |<br>+ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (INTD << D31IP_SIP2) |<br> (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);<br> RCBA32(D30IP) = (NOINT << D30IP_PIP);<br> RCBA32(D29IP) = (INTA << D29IP_E1P);<br>@@ -46,8 +50,10 @@<br> (INTC << D28IP_P3IP) | (INTC << D28IP_P5IP);<br> RCBA32(D27IP) = (INTA << D27IP_ZIP);<br> RCBA32(D26IP) = (INTA << D26IP_E2P);<br>- RCBA32(D25IP) = (NOINT << D25IP_LIP);<br>- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);<br>+ RCBA32(D25IP) = (INTA << D25IP_LIP);<br>+ RCBA32(D22IP) = (INTA << D22IP_MEI1IP) | (NOINT << D22IP_MEI2IP) |<br>+ (NOINT << D22IP_IDERIP) | (NOINT << D22IP_KTIP);<br>+ RCBA32(D20IP) = (INTA << D20IP_XHCIIP);<br> <br> /* Device interrupt route registers */<br> DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);<br>@@ -57,6 +63,7 @@<br> DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);<br> DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);<br> DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);<br>+ DIR_ROUTE(D20IR, PIRQD, PIRQA, PIRQB, PIRQC);<br> <br> /* Enable IOAPIC (generic) */<br> RCBA16(OIC) = 0x0100;<br></pre><p>To view, visit <a href="https://review.coreboot.org/22622">change 22622</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22622"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id14f4e2fb03e0a9149c443487665f6eb04c4d3bd </div>
<div style="display:none"> Gerrit-Change-Number: 22622 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tobias Diedrich <ranma+coreboot@tdiedrich.de> </div>