[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Make use of Intel common DSP block

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22609


Change subject: soc/intel/skylake: Make use of Intel common DSP block
......................................................................

soc/intel/skylake: Make use of Intel common DSP block

TEST=Build and boot soraka/eve.

Change-Id: I8be2a90dc4e4c5eb196af57045d2a46b7f0c9722
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/Makefile.inc
D src/soc/intel/skylake/dsp.c
M src/soc/intel/skylake/include/soc/pci_devs.h
6 files changed, 3 insertions(+), 38 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/22609/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 0c78fab..9fe7681 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2905,6 +2905,7 @@
 #define PCI_DEVICE_ID_INTEL_APL_AUDIO		0x5a98
 #define PCI_DEVICE_ID_INTEL_GLK_AUDIO		0x3198
 #define PCI_DEVICE_ID_INTEL_CNL_AUDIO		0x9dc8
+#define PCI_DEVICE_ID_INTEL_SKL_AUDIO		0x9d70
 
 /* Intel HECI/ME device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_CSE0		0x5a9a
diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c
index 06384c7..5b4f932 100644
--- a/src/soc/intel/common/block/dsp/dsp.c
+++ b/src/soc/intel/common/block/dsp/dsp.c
@@ -29,6 +29,7 @@
 	PCI_DEVICE_ID_INTEL_APL_AUDIO,
 	PCI_DEVICE_ID_INTEL_CNL_AUDIO,
 	PCI_DEVICE_ID_INTEL_GLK_AUDIO,
+	PCI_DEVICE_ID_INTEL_SKL_AUDIO,
 	0,
 };
 
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index e5cc4f7..053239a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -55,6 +55,7 @@
 	select SOC_INTEL_COMMON_BLOCK_CPU
 	select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
 	select SOC_INTEL_COMMON_BLOCK_CSE
+	select SOC_INTEL_COMMON_BLOCK_DSP
 	select SOC_INTEL_COMMON_BLOCK_EBDA
 	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
 	select SOC_INTEL_COMMON_BLOCK_GPIO
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index da45ec5..3a6dd2d 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -46,7 +46,6 @@
 ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c
 ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c
 ramstage-y += cpu.c
-ramstage-y += dsp.c
 ramstage-y += elog.c
 ramstage-y += finalize.c
 ramstage-y += gpio.c
diff --git a/src/soc/intel/skylake/dsp.c b/src/soc/intel/skylake/dsp.c
deleted file mode 100644
index 13051a0..0000000
--- a/src/soc/intel/skylake/dsp.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <soc/ramstage.h>
-
-static struct device_operations dsp_dev_ops = {
-	.read_resources		= &pci_dev_read_resources,
-	.set_resources		= &pci_dev_set_resources,
-	.enable_resources	= &pci_dev_enable_resources,
-	.scan_bus		= &scan_static_bus,
-	.ops_pci		= &soc_pci_ops,
-};
-
-static const struct pci_driver skylake_dsp __pci_driver = {
-	.ops	= &dsp_dev_ops,
-	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device = 0x9d70
-};
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 28f2f39..4fc8807 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -44,10 +44,6 @@
 #define  SA_DEVFN_IGD		_SA_DEVFN(IGD)
 #define  SA_DEV_IGD		_SA_DEV(IGD)
 
-#define SA_DEV_SLOT_DSP		0x04
-#define  SA_DEVFN_DSP		_SA_DEVFN(DSP)
-#define  SA_DEV_DSP		_SA_DEV(DSP)
-
 /* PCH Devices */
 
 #define PCH_DEV_SLOT_ISH	0x13

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8be2a90dc4e4c5eb196af57045d2a46b7f0c9722
Gerrit-Change-Number: 22609
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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