[coreboot-gerrit] Change in coreboot[master]: intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/22603


Change subject: intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c
......................................................................

intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c

Change-Id: Ib1b761fc417f1bb000f408d3bed5e8666963f51d
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/cpu/x86/lapic/apic_timer.c
M src/include/cpu/intel/speedstep.h
M src/mainboard/asus/p5gc-mx/romstage.c
3 files changed, 4 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/22603/1

diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index 254bb07..e218d29 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -77,13 +77,13 @@
 		switch (c.x86_model) {
 		case 0x2:
 			car_set_var(g_timer_fsb,
-				f2x_fsb[(rdmsr(0x2c).lo >> 16) & 7]);
+				f2x_fsb[(rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 16) & 7]);
 			return 0;
 		case 0x3:
 		case 0x4:
 		case 0x6:
 			car_set_var(g_timer_fsb,
-				core2_fsb[(rdmsr(0x2c).lo >> 16) & 7]);
+				core2_fsb[(rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 16) & 7]);
 			return 0;
 		}  /* default: fallthrough */
 	default:
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index 40234d5..003034c 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -40,6 +40,7 @@
 #define IA32_PERF_CTL     0x199
 #define MSR_THERM2_CTL    0x19D
 #define IA32_MISC_ENABLES 0x1A0
+#define MSR_EBC_FREQUENCY_ID	0x2c
 #define MSR_FSB_FREQ		0xcd
 #define MSR_FSB_CLOCK_VCC	0xce
 #define MSR_PMG_CST_CONFIG_CONTROL	0xe2
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index a29478c..69db496 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -94,7 +94,7 @@
 
 	/* Netburst */
 	if (((eax >> 8) & 0xf) == 0xf) {
-		msr = rdmsr(0x2c);
+		msr = rdmsr(MSR_EBC_FREQUENCY_ID);
 		fsbcfg = (msr.lo >> 16) & 0x7;
 	} else { /* Intel Core 2 */
 		msr = rdmsr(MSR_FSB_FREQ);

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib1b761fc417f1bb000f408d3bed5e8666963f51d
Gerrit-Change-Number: 22603
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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