<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22603">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c<br><br>Change-Id: Ib1b761fc417f1bb000f408d3bed5e8666963f51d<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/x86/lapic/apic_timer.c<br>M src/include/cpu/intel/speedstep.h<br>M src/mainboard/asus/p5gc-mx/romstage.c<br>3 files changed, 4 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/22603/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c<br>index 254bb07..e218d29 100644<br>--- a/src/cpu/x86/lapic/apic_timer.c<br>+++ b/src/cpu/x86/lapic/apic_timer.c<br>@@ -77,13 +77,13 @@<br>           switch (c.x86_model) {<br>                case 0x2:<br>                     car_set_var(g_timer_fsb,<br>-                             f2x_fsb[(rdmsr(0x2c).lo >> 16) & 7]);<br>+                              f2x_fsb[(rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 16) & 7]);<br>                       return 0;<br>             case 0x3:<br>             case 0x4:<br>             case 0x6:<br>                     car_set_var(g_timer_fsb,<br>-                             core2_fsb[(rdmsr(0x2c).lo >> 16) & 7]);<br>+                            core2_fsb[(rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 16) & 7]);<br>                     return 0;<br>             }  /* default: fallthrough */<br>         default:<br>diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h<br>index 40234d5..003034c 100644<br>--- a/src/include/cpu/intel/speedstep.h<br>+++ b/src/include/cpu/intel/speedstep.h<br>@@ -40,6 +40,7 @@<br> #define IA32_PERF_CTL     0x199<br> #define MSR_THERM2_CTL    0x19D<br> #define IA32_MISC_ENABLES 0x1A0<br>+#define MSR_EBC_FREQUENCY_ID   0x2c<br> #define MSR_FSB_FREQ             0xcd<br> #define MSR_FSB_CLOCK_VCC        0xce<br> #define MSR_PMG_CST_CONFIG_CONTROL       0xe2<br>diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c<br>index a29478c..69db496 100644<br>--- a/src/mainboard/asus/p5gc-mx/romstage.c<br>+++ b/src/mainboard/asus/p5gc-mx/romstage.c<br>@@ -94,7 +94,7 @@<br> <br>       /* Netburst */<br>        if (((eax >> 8) & 0xf) == 0xf) {<br>-           msr = rdmsr(0x2c);<br>+           msr = rdmsr(MSR_EBC_FREQUENCY_ID);<br>            fsbcfg = (msr.lo >> 16) & 0x7;<br>      } else { /* Intel Core 2 */<br>           msr = rdmsr(MSR_FSB_FREQ);<br></pre><p>To view, visit <a href="https://review.coreboot.org/22603">change 22603</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22603"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib1b761fc417f1bb000f408d3bed5e8666963f51d </div>
<div style="display:none"> Gerrit-Change-Number: 22603 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>