[coreboot-gerrit] Change in coreboot[master]: Replace msr(0x198) with msr(IA32_PERF_STATUS)

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/22585


Change subject: Replace msr(0x198) with msr(IA32_PERF_STATUS)
......................................................................

Replace msr(0x198) with msr(IA32_PERF_STATUS)

Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/cpu/intel/model_6ex/model_6ex_init.c
M src/cpu/intel/model_6fx/model_6fx_init.c
M src/cpu/intel/speedstep/speedstep.c
M src/include/cpu/intel/speedstep.h
M src/mainboard/intel/eagleheights/romstage.c
M src/mainboard/intel/mtarvon/romstage.c
M src/northbridge/intel/i945/udelay.c
7 files changed, 9 insertions(+), 9 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/22585/1

diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 6e5b339..96830c4 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -86,7 +86,7 @@
 	wrmsr(IA32_MISC_ENABLE, msr);
 
 	// set maximum CPU speed
-	msr = rdmsr(IA32_PERF_STS);
+	msr = rdmsr(IA32_PERF_STATUS);
 	int busratio_max = (msr.hi >> (40-32)) & 0x1f;
 
 	msr = rdmsr(IA32_PLATFORM_ID);
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index b5a68cc..a1433f6 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -94,7 +94,7 @@
 	wrmsr(IA32_MISC_ENABLE, msr);
 
 	// set maximum CPU speed
-	msr = rdmsr(IA32_PERF_STS);
+	msr = rdmsr(IA32_PERF_STATUS);
 	int busratio_max = (msr.hi >> (40-32)) & 0x1f;
 
 	msr = rdmsr(IA32_PLATFORM_ID);
diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c
index 96ac8e5..441f2a3 100644
--- a/src/cpu/intel/speedstep/speedstep.c
+++ b/src/cpu/intel/speedstep/speedstep.c
@@ -55,15 +55,15 @@
 
 	/* Read normal maximum parameters. */
 	/* Newer CPUs provide the normal maximum settings in
-	   IA32_PLATFORM_ID. The values in IA32_PERF_STS change
+	   IA32_PLATFORM_ID. The values in IA32_PERF_STATUS change
 	   when using turbo mode. */
 	msr = rdmsr(IA32_PLATFORM_ID);
 	params->max = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask);
 	if (cpu_id == 0x006e) {
 		/* Looks like Yonah CPUs don't have the frequency ratio in
-		   IA32_PLATFORM_ID. Use IA32_PERF_STS instead, the reading
+		   IA32_PLATFORM_ID. Use IA32_PERF_STATUS instead, the reading
 		   should be reliable as those CPUs don't have turbo mode. */
-		msr = rdmsr(IA32_PERF_STS);
+		msr = rdmsr(IA32_PERF_STATUS);
 		params->max.ratio = (msr.hi & SPEEDSTEP_RATIO_VALUE_MASK)
 						>> SPEEDSTEP_RATIO_SHIFT;
 	}
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index 40234d5..bcf6918 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -36,7 +36,7 @@
 
 /* Speedstep related MSRs */
 #define IA32_PLATFORM_ID  0x017
-#define IA32_PERF_STS     0x198
+#define IA32_PERF_STATUS     0x198
 #define IA32_PERF_CTL     0x199
 #define MSR_THERM2_CTL    0x19D
 #define IA32_MISC_ENABLES 0x1A0
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index c254f17..21313eb 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -171,7 +171,7 @@
 		 * bits 47:32, where BUS_RATIO_MAX and VID_MAX
 		 * are encoded
 		 */
-		msr = rdmsr(IA32_PERF_STS);
+		msr = rdmsr(IA32_PERF_STATUS);
 		perf = msr.hi & 0x0000ffff;
 
 		/* Write VID_MAX & BUS_RATIO_MAX to
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index cb3e870..13f425e 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -100,7 +100,7 @@
 
 	/* Set CPU frequency/voltage to maximum */
 	/* FIXME: move to Pentium M init code */
-	msr = rdmsr(0x198);
+	msr = rdmsr(IA32_PERF_STATUS);
 	perf = msr.hi & 0xffff;
 	msr = rdmsr(0x199);
 	msr.lo &= 0xffff0000;
diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index 90f2638..8447453 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -56,7 +56,7 @@
 		break;
 	}
 
-	msr = rdmsr(0x198);
+	msr = rdmsr(IA32_PERF_STATUS);
 	divisor = (msr.hi >> 8) & 0x1f;
 
 	d = (fsb * divisor) / 4;	/* CPU clock is always a quarter. */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace
Gerrit-Change-Number: 22585
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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