<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22585">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Replace msr(0x198) with msr(IA32_PERF_STATUS)<br><br>Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/model_6ex/model_6ex_init.c<br>M src/cpu/intel/model_6fx/model_6fx_init.c<br>M src/cpu/intel/speedstep/speedstep.c<br>M src/include/cpu/intel/speedstep.h<br>M src/mainboard/intel/eagleheights/romstage.c<br>M src/mainboard/intel/mtarvon/romstage.c<br>M src/northbridge/intel/i945/udelay.c<br>7 files changed, 9 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/22585/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c<br>index 6e5b339..96830c4 100644<br>--- a/src/cpu/intel/model_6ex/model_6ex_init.c<br>+++ b/src/cpu/intel/model_6ex/model_6ex_init.c<br>@@ -86,7 +86,7 @@<br> wrmsr(IA32_MISC_ENABLE, msr);<br> <br> // set maximum CPU speed<br>- msr = rdmsr(IA32_PERF_STS);<br>+ msr = rdmsr(IA32_PERF_STATUS);<br> int busratio_max = (msr.hi >> (40-32)) & 0x1f;<br> <br> msr = rdmsr(IA32_PLATFORM_ID);<br>diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c<br>index b5a68cc..a1433f6 100644<br>--- a/src/cpu/intel/model_6fx/model_6fx_init.c<br>+++ b/src/cpu/intel/model_6fx/model_6fx_init.c<br>@@ -94,7 +94,7 @@<br> wrmsr(IA32_MISC_ENABLE, msr);<br> <br> // set maximum CPU speed<br>- msr = rdmsr(IA32_PERF_STS);<br>+ msr = rdmsr(IA32_PERF_STATUS);<br> int busratio_max = (msr.hi >> (40-32)) & 0x1f;<br> <br> msr = rdmsr(IA32_PLATFORM_ID);<br>diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c<br>index 96ac8e5..441f2a3 100644<br>--- a/src/cpu/intel/speedstep/speedstep.c<br>+++ b/src/cpu/intel/speedstep/speedstep.c<br>@@ -55,15 +55,15 @@<br> <br> /* Read normal maximum parameters. */<br> /* Newer CPUs provide the normal maximum settings in<br>- IA32_PLATFORM_ID. The values in IA32_PERF_STS change<br>+ IA32_PLATFORM_ID. The values in IA32_PERF_STATUS change<br> when using turbo mode. */<br> msr = rdmsr(IA32_PLATFORM_ID);<br> params->max = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask);<br> if (cpu_id == 0x006e) {<br> /* Looks like Yonah CPUs don't have the frequency ratio in<br>- IA32_PLATFORM_ID. Use IA32_PERF_STS instead, the reading<br>+ IA32_PLATFORM_ID. Use IA32_PERF_STATUS instead, the reading<br> should be reliable as those CPUs don't have turbo mode. */<br>- msr = rdmsr(IA32_PERF_STS);<br>+ msr = rdmsr(IA32_PERF_STATUS);<br> params->max.ratio = (msr.hi & SPEEDSTEP_RATIO_VALUE_MASK)<br> >> SPEEDSTEP_RATIO_SHIFT;<br> }<br>diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h<br>index 40234d5..bcf6918 100644<br>--- a/src/include/cpu/intel/speedstep.h<br>+++ b/src/include/cpu/intel/speedstep.h<br>@@ -36,7 +36,7 @@<br> <br> /* Speedstep related MSRs */<br> #define IA32_PLATFORM_ID 0x017<br>-#define IA32_PERF_STS 0x198<br>+#define IA32_PERF_STATUS 0x198<br> #define IA32_PERF_CTL 0x199<br> #define MSR_THERM2_CTL 0x19D<br> #define IA32_MISC_ENABLES 0x1A0<br>diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c<br>index c254f17..21313eb 100644<br>--- a/src/mainboard/intel/eagleheights/romstage.c<br>+++ b/src/mainboard/intel/eagleheights/romstage.c<br>@@ -171,7 +171,7 @@<br> * bits 47:32, where BUS_RATIO_MAX and VID_MAX<br> * are encoded<br> */<br>- msr = rdmsr(IA32_PERF_STS);<br>+ msr = rdmsr(IA32_PERF_STATUS);<br> perf = msr.hi & 0x0000ffff;<br> <br> /* Write VID_MAX & BUS_RATIO_MAX to<br>diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c<br>index cb3e870..13f425e 100644<br>--- a/src/mainboard/intel/mtarvon/romstage.c<br>+++ b/src/mainboard/intel/mtarvon/romstage.c<br>@@ -100,7 +100,7 @@<br> <br> /* Set CPU frequency/voltage to maximum */<br> /* FIXME: move to Pentium M init code */<br>- msr = rdmsr(0x198);<br>+ msr = rdmsr(IA32_PERF_STATUS);<br> perf = msr.hi & 0xffff;<br> msr = rdmsr(0x199);<br> msr.lo &= 0xffff0000;<br>diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c<br>index 90f2638..8447453 100644<br>--- a/src/northbridge/intel/i945/udelay.c<br>+++ b/src/northbridge/intel/i945/udelay.c<br>@@ -56,7 +56,7 @@<br> break;<br> }<br> <br>- msr = rdmsr(0x198);<br>+ msr = rdmsr(IA32_PERF_STATUS);<br> divisor = (msr.hi >> 8) & 0x1f;<br> <br> d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */<br></pre><p>To view, visit <a href="https://review.coreboot.org/22585">change 22585</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22585"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace </div>
<div style="display:none"> Gerrit-Change-Number: 22585 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>