[coreboot-gerrit] Change in coreboot[master]: google/fizz: Disable cr50 i2c lines

[Shelley Chen (Code Review)]

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/22576


Change subject: google/fizz: Disable cr50 i2c lines
......................................................................

google/fizz: Disable cr50 i2c lines

As cr50 has now switched to using SPI, no need to enable the i2c
anymore.

BUG=b:69374421
BRANCH=None
TEST=test on fizz celeron.  Make sure /dev/tpm0 created on (many)
     reboots.  cat /proc/interrupts.  Make sure # interrupts for 16
     after booting is reasonable (not > 10k).  and idma64.0,
     i2c_designware.0 are not listed with that line anymore.  Should
     look something like:

     16: 1174 0 IO-APIC 16-fasteoi i801_smbus, snd_soc_skl, AudioDSP

Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b
Signed-off-by: Shelley Chen <shchen at chromium.org>
---
M src/mainboard/google/fizz/devicetree.cb
1 file changed, 7 insertions(+), 21 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/22576/1

diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 73a5c50..df664b2 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -233,17 +233,11 @@
 		 .early_init = 1,
 	}"
 
-	# Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
-	# for TPM communication before memory is up.
-	register "i2c[1]" = "{
-		 .early_init = 1,
-	}"
-
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
 		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
@@ -273,18 +267,10 @@
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
-		device pci 15.0 on
-		end # I2C #0
-		device pci 15.1 on
-			chip drivers/i2c/tpm
-				register "hid" = ""GOOG0005""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
-				device i2c 50 on end
-			end
-		end # I2C #1
-		device pci 15.2 on  end # I2C #2
-		device pci 15.3 off
-		end # I2C #3
+		device pci 15.0 off end # I2C #0
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
 		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b
Gerrit-Change-Number: 22576
Gerrit-PatchSet: 1
Gerrit-Owner: Shelley Chen <shchen at google.com>
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