<p>Shelley Chen has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22576">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/fizz: Disable cr50 i2c lines<br><br>As cr50 has now switched to using SPI, no need to enable the i2c<br>anymore.<br><br>BUG=b:69374421<br>BRANCH=None<br>TEST=test on fizz celeron. Make sure /dev/tpm0 created on (many)<br> reboots. cat /proc/interrupts. Make sure # interrupts for 16<br> after booting is reasonable (not > 10k). and idma64.0,<br> i2c_designware.0 are not listed with that line anymore. Should<br> look something like:<br><br> 16: 1174 0 IO-APIC 16-fasteoi i801_smbus, snd_soc_skl, AudioDSP<br><br>Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b<br>Signed-off-by: Shelley Chen <shchen@chromium.org><br>---<br>M src/mainboard/google/fizz/devicetree.cb<br>1 file changed, 7 insertions(+), 21 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/22576/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb<br>index 73a5c50..df664b2 100644<br>--- a/src/mainboard/google/fizz/devicetree.cb<br>+++ b/src/mainboard/google/fizz/devicetree.cb<br>@@ -233,17 +233,11 @@<br> .early_init = 1,<br> }"<br> <br>- # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR<br>- # for TPM communication before memory is up.<br>- register "i2c[1]" = "{<br>- .early_init = 1,<br>- }"<br>-<br> # Must leave UART0 enabled or SD/eMMC will not work as PCI<br> register "SerialIoDevMode" = "{<br>- [PchSerialIoIndexI2C0] = PchSerialIoPci,<br>- [PchSerialIoIndexI2C1] = PchSerialIoPci,<br>- [PchSerialIoIndexI2C2] = PchSerialIoPci,<br>+ [PchSerialIoIndexI2C0] = PchSerialIoDisabled,<br>+ [PchSerialIoIndexI2C1] = PchSerialIoDisabled,<br>+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,<br> [PchSerialIoIndexI2C3] = PchSerialIoDisabled,<br> [PchSerialIoIndexI2C4] = PchSerialIoDisabled,<br> [PchSerialIoIndexI2C5] = PchSerialIoPci,<br>@@ -273,18 +267,10 @@<br> device pci 14.0 on end # USB xHCI<br> device pci 14.1 off end # USB xDCI (OTG)<br> device pci 14.2 on end # Thermal Subsystem<br>- device pci 15.0 on<br>- end # I2C #0<br>- device pci 15.1 on<br>- chip drivers/i2c/tpm<br>- register "hid" = ""GOOG0005""<br>- register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"<br>- device i2c 50 on end<br>- end<br>- end # I2C #1<br>- device pci 15.2 on end # I2C #2<br>- device pci 15.3 off<br>- end # I2C #3<br>+ device pci 15.0 off end # I2C #0<br>+ device pci 15.1 off end # I2C #1<br>+ device pci 15.2 off end # I2C #2<br>+ device pci 15.3 off end # I2C #3<br> device pci 16.0 on end # Management Engine Interface 1<br> device pci 16.1 off end # Management Engine Interface 2<br> device pci 16.2 off end # Management Engine IDE-R<br></pre><p>To view, visit <a href="https://review.coreboot.org/22576">change 22576</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22576"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b </div>
<div style="display:none"> Gerrit-Change-Number: 22576 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Shelley Chen <shchen@google.com> </div>