[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Make use of Intel common PMC common block

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22566


Change subject: soc/intel/cannonlake: Make use of Intel common PMC common block
......................................................................

soc/intel/cannonlake: Make use of Intel common PMC common block

TEST=Build and boot cannonlake rvp.

Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/cannonlake/pmc.c
1 file changed, 12 insertions(+), 83 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/22566/1

diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index a0d816e..66ec844 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -18,73 +18,21 @@
 #include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include <arch/acpi.h>
-#include <cpu/cpu.h>
-#include <intelblocks/pcr.h>
+#include <intelblocks/pmc.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
-#include <pc80/mc146818rtc.h>
-#include <string.h>
-#include <soc/gpio.h>
-#include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
-#include <cpu/x86/smm.h>
-#include <soc/pcr_ids.h>
-#include <soc/ramstage.h>
-#include <security/vboot/vbnv.h>
-#include <security/vboot/vbnv_layout.h>
 
-static void pch_pmc_add_mmio_resources(device_t dev)
+/* Fill up PMC resource structure */
+void soc_pch_pmc_get_resources(struct pmc_resource_config *cfg)
 {
-	struct resource *res;
-
-	/* Memory-mmapped I/O registers. */
-	res = new_resource(dev, PWRMBASE);
-	res->base = PCH_PWRM_BASE_ADDRESS;
-	res->size = PCH_PWRM_BASE_SIZE;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
-			IORESOURCE_FIXED | IORESOURCE_RESERVE;
-}
-
-static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index)
-{
-	struct resource *res;
-	res = new_resource(dev, index);
-	res->base = base;
-	res->size = size;
-	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static void pch_pmc_add_io_resources(device_t dev)
-{
-	/* PMBASE */
-	pch_pmc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
-}
-
-static void pch_pmc_read_resources(device_t dev)
-{
-	/* Get the normal PCI resources of this device. */
-	pci_dev_read_resources(dev);
-
-	/* Add non-standard MMIO resources. */
-	pch_pmc_add_mmio_resources(dev);
-
-	/* Add IO resources. */
-	pch_pmc_add_io_resources(dev);
-}
-
-static void pch_set_acpi_mode(void)
-{
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
-		printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
-		outb(APM_CNT_ACPI_DISABLE, APM_CNT);
-		printk(BIOS_DEBUG, "done.\n");
-	}
+	cfg->pwrmbase_offset = PWRMBASE;
+	cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS;
+	cfg->pwrmbase_size = PCH_PWRM_BASE_SIZE;
+	cfg->abase_offset = ABASE;
+	cfg->abase_addr = ACPI_BASE_ADDRESS;
+	cfg->abase_size = ACPI_BASE_SIZE;
 }
 
 static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
@@ -128,37 +76,18 @@
 	write32(pmcbase + DSX_CFG, reg);
 }
 
-static void pmc_init(struct device *dev)
+void pmc_init(struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	const config_t *config = dev->chip_info;
 
 	rtc_init();
 
 	/* Initialize power management */
 	pmc_gpe_init();
 
-	pch_set_acpi_mode();
+	pmc_set_acpi_mode();
 
 	config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
 	config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
 	config_deep_sx(config->deep_sx_config);
 }
-
-static struct device_operations device_ops = {
-	.read_resources		= &pch_pmc_read_resources,
-	.set_resources		= &pci_dev_set_resources,
-	.enable_resources	= &pci_dev_enable_resources,
-	.init			= &pmc_init,
-	.scan_bus		= &scan_lpc_bus,
-};
-
-static const unsigned short pci_device_ids[] = {
-	PCI_DEVICE_ID_INTEL_CNL_PMC,
-	0
-};
-
-static const struct pci_driver pch_lpc __pci_driver = {
-	.ops	 = &device_ops,
-	.vendor	 = PCI_VENDOR_ID_INTEL,
-	.devices = pci_device_ids,
-};

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4
Gerrit-Change-Number: 22566
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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