<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22566">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Make use of Intel common PMC common block<br><br>TEST=Build and boot cannonlake rvp.<br><br>Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/cannonlake/pmc.c<br>1 file changed, 12 insertions(+), 83 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/22566/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c<br>index a0d816e..66ec844 100644<br>--- a/src/soc/intel/cannonlake/pmc.c<br>+++ b/src/soc/intel/cannonlake/pmc.c<br>@@ -18,73 +18,21 @@<br> #include <chip.h><br> #include <console/console.h><br> #include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <arch/io.h><br>-#include <arch/ioapic.h><br>-#include <arch/acpi.h><br>-#include <cpu/cpu.h><br>-#include <intelblocks/pcr.h><br>+#include <intelblocks/pmc.h><br> #include <intelblocks/pmclib.h><br> #include <intelblocks/rtc.h><br>-#include <pc80/mc146818rtc.h><br>-#include <string.h><br>-#include <soc/gpio.h><br>-#include <soc/iomap.h><br> #include <soc/pci_devs.h><br> #include <soc/pm.h><br>-#include <cpu/x86/smm.h><br>-#include <soc/pcr_ids.h><br>-#include <soc/ramstage.h><br>-#include <security/vboot/vbnv.h><br>-#include <security/vboot/vbnv_layout.h><br> <br>-static void pch_pmc_add_mmio_resources(device_t dev)<br>+/* Fill up PMC resource structure */<br>+void soc_pch_pmc_get_resources(struct pmc_resource_config *cfg)<br> {<br>-      struct resource *res;<br>-<br>-     /* Memory-mmapped I/O registers. */<br>-  res = new_resource(dev, PWRMBASE);<br>-   res->base = PCH_PWRM_BASE_ADDRESS;<br>-        res->size = PCH_PWRM_BASE_SIZE;<br>-   res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |<br>-                       IORESOURCE_FIXED | IORESOURCE_RESERVE;<br>-}<br>-<br>-static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index)<br>-{<br>- struct resource *res;<br>-        res = new_resource(dev, index);<br>-      res->base = base;<br>- res->size = size;<br>- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-}<br>-<br>-static void pch_pmc_add_io_resources(device_t dev)<br>-{<br>-      /* PMBASE */<br>- pch_pmc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);<br>-}<br>-<br>-static void pch_pmc_read_resources(device_t dev)<br>-{<br>-        /* Get the normal PCI resources of this device. */<br>-   pci_dev_read_resources(dev);<br>-<br>-      /* Add non-standard MMIO resources. */<br>-       pch_pmc_add_mmio_resources(dev);<br>-<br>-  /* Add IO resources. */<br>-      pch_pmc_add_io_resources(dev);<br>-}<br>-<br>-static void pch_set_acpi_mode(void)<br>-{<br>-      if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {<br>-           printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");<br>-          outb(APM_CNT_ACPI_DISABLE, APM_CNT);<br>-         printk(BIOS_DEBUG, "done.\n");<br>-     }<br>+    cfg->pwrmbase_offset = PWRMBASE;<br>+  cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS;<br>+       cfg->pwrmbase_size = PCH_PWRM_BASE_SIZE;<br>+  cfg->abase_offset = ABASE;<br>+        cfg->abase_addr = ACPI_BASE_ADDRESS;<br>+      cfg->abase_size = ACPI_BASE_SIZE;<br> }<br> <br> static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)<br>@@ -128,37 +76,18 @@<br>    write32(pmcbase + DSX_CFG, reg);<br> }<br> <br>-static void pmc_init(struct device *dev)<br>+void pmc_init(struct device *dev)<br> {<br>-   config_t *config = dev->chip_info;<br>+        const config_t *config = dev->chip_info;<br> <br>        rtc_init();<br> <br>        /* Initialize power management */<br>     pmc_gpe_init();<br> <br>-   pch_set_acpi_mode();<br>+ pmc_set_acpi_mode();<br> <br>       config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);<br>   config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);<br>   config_deep_sx(config->deep_sx_config);<br> }<br>-<br>-static struct device_operations device_ops = {<br>-   .read_resources         = &pch_pmc_read_resources,<br>-       .set_resources          = &pci_dev_set_resources,<br>-        .enable_resources       = &pci_dev_enable_resources,<br>-     .init                   = &pmc_init,<br>-     .scan_bus               = &scan_lpc_bus,<br>-};<br>-<br>-static const unsigned short pci_device_ids[] = {<br>-      PCI_DEVICE_ID_INTEL_CNL_PMC,<br>- 0<br>-};<br>-<br>-static const struct pci_driver pch_lpc __pci_driver = {<br>-  .ops     = &device_ops,<br>-  .vendor  = PCI_VENDOR_ID_INTEL,<br>-      .devices = pci_device_ids,<br>-};<br></pre><p>To view, visit <a href="https://review.coreboot.org/22566">change 22566</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22566"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4 </div>
<div style="display:none"> Gerrit-Change-Number: 22566 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>