[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge/southbridge.c: Fix table intr_types[]

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22548


Change subject: amd/stoneyridge/southbridge.c: Fix table intr_types[]
......................................................................

amd/stoneyridge/southbridge.c: Fix table intr_types[]

Table intr_types is based on Hudson. Stoneyridge APIC is organized
differently, some strings represent APIC registers that don't exist
in Stoneyridge, while some of Stoneyridge APIC registers are not
represented in the table. Fix the table, paying attention to the
correct index for each valid register.

amd_pci_int_defs.h must be fixed to reflect the new table.

BUG=b:62200834

Change-Id: I0f0921e0a540a31b1fb7ec3940006d632cb25f55
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h
M src/soc/amd/stoneyridge/southbridge.c
2 files changed, 8 insertions(+), 15 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/22548/1

diff --git a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h
index f803a44..5f457a6 100644
--- a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h
+++ b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h
@@ -45,23 +45,17 @@
 #define PIRQ_ASF	0x12	/* ASF */
 #define PIRQ_HDA	0x13	/* HDA		14h.2 */
 #define PIRQ_FC		0x14	/* FC */
-#define PIRQ_GEC	0x15	/* GEC */
 #define PIRQ_PMON	0x16	/* Performance Monitor */
 #define PIRQ_SD		0x17	/* SD */
+#define PIRQ_SDIO	0x1a	/* SDIO */
 #define PIRQ_IMC0	0x20	/* IMC INT0 */
 #define PIRQ_IMC1	0x21	/* IMC INT1 */
 #define PIRQ_IMC2	0x22	/* IMC INT2 */
 #define PIRQ_IMC3	0x23	/* IMC INT3 */
 #define PIRQ_IMC4	0x24	/* IMC INT4 */
 #define PIRQ_IMC5	0x25	/* IMC INT5 */
-#define PIRQ_OHCI1	0x30	/* USB OHCI	12h.0 */
-#define PIRQ_EHCI1	0x31	/* USB EHCI	12h.2 */
-#define PIRQ_OHCI2	0x32	/* USB OHCI	13h.0 */
-#define PIRQ_EHCI2	0x33	/* USB EHCI	13h.2 */
-#define PIRQ_OHCI3	0x34	/* USB OHCI	16h.0 */
-#define PIRQ_EHCI3	0x35	/* USB EHCI	16h.2 */
-#define PIRQ_OHCI4	0x36	/* USB OHCI	14h.5 */
-#define PIRQ_IDE	0x40	/* IDE		14h.1 */
+#define PIRQ_EHCI	0x30	/* USB EHCI	12h.0 */
+#define PIRQ_XHCI	0x34	/* USB XHCI	10h.0 */
 #define PIRQ_SATA	0x41	/* SATA		11h.0 */
 #define PIRQ_GPIO	0x62	/* GPIO Controller Interrupt */
 #define PIRQ_I2C0	0x70
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index ac5bcf5..f4dd7fb 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -47,14 +47,13 @@
 			"Ser IRQ INTC",
 		 "Ser IRQ INTD",
 	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t",
-			"GEC\t", "PerMon\t", "SD\t\t",
+	[0x16] = "PerMon\t", "SD\t\t",
+	[0x1a] = "SDIO\t",
 	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t",
 			"IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
-	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB",
-			"Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
-	[0x40] = "IDE\t", "SATA\t",
-	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t",
-			"GPPInt3\t",
+	[0x30] = "EHCI\t",
+	[0x34] = "XHCI\t",
+	[0x41] = "SATA\t",
 	[0x62] = "GPIO\t",
 	[0x70] = "I2C0\t", "I2C1\t", "I2C2\t",
 			"I2C3\t", "UART0\t", "UART1\t",

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0f0921e0a540a31b1fb7ec3940006d632cb25f55
Gerrit-Change-Number: 22548
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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