<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22548">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge/southbridge.c: Fix table intr_types[]<br><br>Table intr_types is based on Hudson. Stoneyridge APIC is organized<br>differently, some strings represent APIC registers that don't exist<br>in Stoneyridge, while some of Stoneyridge APIC registers are not<br>represented in the table. Fix the table, paying attention to the<br>correct index for each valid register.<br><br>amd_pci_int_defs.h must be fixed to reflect the new table.<br><br>BUG=b:62200834<br><br>Change-Id: I0f0921e0a540a31b1fb7ec3940006d632cb25f55<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 8 insertions(+), 15 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/22548/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h<br>index f803a44..5f457a6 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h<br>@@ -45,23 +45,17 @@<br> #define PIRQ_ASF     0x12    /* ASF */<br> #define PIRQ_HDA    0x13    /* HDA          14h.2 */<br> #define PIRQ_FC              0x14    /* FC */<br>-#define PIRQ_GEC     0x15    /* GEC */<br> #define PIRQ_PMON   0x16    /* Performance Monitor */<br> #define PIRQ_SD             0x17    /* SD */<br>+#define PIRQ_SDIO    0x1a    /* SDIO */<br> #define PIRQ_IMC0  0x20    /* IMC INT0 */<br> #define PIRQ_IMC1      0x21    /* IMC INT1 */<br> #define PIRQ_IMC2      0x22    /* IMC INT2 */<br> #define PIRQ_IMC3      0x23    /* IMC INT3 */<br> #define PIRQ_IMC4      0x24    /* IMC INT4 */<br> #define PIRQ_IMC5      0x25    /* IMC INT5 */<br>-#define PIRQ_OHCI1     0x30    /* USB OHCI     12h.0 */<br>-#define PIRQ_EHCI1   0x31    /* USB EHCI     12h.2 */<br>-#define PIRQ_OHCI2   0x32    /* USB OHCI     13h.0 */<br>-#define PIRQ_EHCI2   0x33    /* USB EHCI     13h.2 */<br>-#define PIRQ_OHCI3   0x34    /* USB OHCI     16h.0 */<br>-#define PIRQ_EHCI3   0x35    /* USB EHCI     16h.2 */<br>-#define PIRQ_OHCI4   0x36    /* USB OHCI     14h.5 */<br>-#define PIRQ_IDE     0x40    /* IDE          14h.1 */<br>+#define PIRQ_EHCI    0x30    /* USB EHCI     12h.0 */<br>+#define PIRQ_XHCI    0x34    /* USB XHCI     10h.0 */<br> #define PIRQ_SATA    0x41    /* SATA         11h.0 */<br> #define PIRQ_GPIO    0x62    /* GPIO Controller Interrupt */<br> #define PIRQ_I2C0     0x70<br>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c<br>index ac5bcf5..f4dd7fb 100644<br>--- a/src/soc/amd/stoneyridge/southbridge.c<br>+++ b/src/soc/amd/stoneyridge/southbridge.c<br>@@ -47,14 +47,13 @@<br>                        "Ser IRQ INTC",<br>              "Ser IRQ INTD",<br>    [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t",<br>-                  "GEC\t", "PerMon\t", "SD\t\t",<br>+ [0x16] = "PerMon\t", "SD\t\t",<br>+   [0x1a] = "SDIO\t",<br>  [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t",<br>                      "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",<br>-      [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB",<br>-                     "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",<br>-        [0x40] = "IDE\t", "SATA\t",<br>-      [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t",<br>-                        "GPPInt3\t",<br>+       [0x30] = "EHCI\t",<br>+ [0x34] = "XHCI\t",<br>+ [0x41] = "SATA\t",<br>  [0x62] = "GPIO\t",<br>  [0x70] = "I2C0\t", "I2C1\t", "I2C2\t",<br>                  "I2C3\t", "UART0\t", "UART1\t",<br></pre><p>To view, visit <a href="https://review.coreboot.org/22548">change 22548</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22548"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0f0921e0a540a31b1fb7ec3940006d632cb25f55 </div>
<div style="display:none"> Gerrit-Change-Number: 22548 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>