[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Use bridge_silicon_revision in all places
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Mon Nov 20 10:33:35 CET 2017
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/22531
Change subject: nb/intel/sandybridge: Use bridge_silicon_revision in all places
......................................................................
nb/intel/sandybridge: Use bridge_silicon_revision in all places
* Move bridge_silicon_revision to common.c
* Use bridge_silicon_revision instead of custom methods
* Get rid of unused macros
Change-Id: Iba342dc1830102f3751c89c2b5736f4477c9f4e4
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/northbridge/intel/sandybridge/common.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_common.h
M src/northbridge/intel/sandybridge/sandybridge.h
8 files changed, 41 insertions(+), 70 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/22531/1
diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c
index b5a3544..059dc1e 100644
--- a/src/northbridge/intel/sandybridge/common.c
+++ b/src/northbridge/intel/sandybridge/common.c
@@ -38,3 +38,23 @@
return platform_mobile;
}
}
+
+int bridge_silicon_revision(void)
+{
+ const uint8_t stepping = cpuid_eax(1) & 0xf;
+
+ const uint8_t bridge_id = pci_read_config16(
+#if defined(__SIMPLE_DEVICE__)
+ PCI_DEVFN(0, 0),
+#else
+ dev_find_slot(0, PCI_DEVFN(0, 0)),
+#endif
+ PCI_DEVICE_ID) & 0xf0;
+
+ return bridge_id | stepping;
+}
+
+int is_sandy_bridge_cpu(void)
+{
+ return (bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB;
+}
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 61b9008..3ec660d 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -348,7 +348,7 @@
gtt_poll(0x130040, (1 << 0), (1 << 0));
}
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ if (is_sandy_bridge_cpu()) {
/* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
reg32 = gtt_read(0x42004);
reg32 |= (1 << 14) | (1 << 15);
@@ -364,7 +364,7 @@
/* 2: Get GT SKU from GTT+0x911c[13] */
reg32 = gtt_read(0x911c);
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ if (is_sandy_bridge_cpu()) {
if (reg32 & (1 << 13)) {
printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n");
gtt_write_powermeter(snb_pm_gt1);
@@ -421,8 +421,8 @@
gtt_write(0xa180, reg32);
/* 6a: for SnB step D2+ only */
- if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
- (bridge_silicon_revision() >= SNB_STEP_D2)) {
+ if (is_sandy_bridge_cpu() &&
+ (bridge_silicon_revision() >= SNB_STEP_D2)) {
reg32 = gtt_read(0x9400);
reg32 |= (1 << 7);
gtt_write(0x9400, reg32);
@@ -434,7 +434,7 @@
gtt_poll(0x941c, (1 << 1), (0 << 1));
}
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ if (!is_sandy_bridge_cpu()) {
reg32 = gtt_read(0x907c);
reg32 |= (1 << 16);
gtt_write(0x907c, reg32);
@@ -485,7 +485,7 @@
gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */
/* 11a: Enable Render Standby (RC6) */
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ if (!is_sandy_bridge_cpu()) {
/*
* IvyBridge should also support DeepRenderStandby.
*
diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index 5e8c188..742264d 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -133,9 +133,8 @@
if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
return 0;
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ if (!is_sandy_bridge_cpu())
return i915lightup_ivy(info, physbase, piobase, mmio, lfb);
- }
write32(mmio + 0x00070080, 0x00000000);
write32(mmio + DSPCNTR(0), 0x00000000);
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 9fed17e..66cf7b4 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -33,23 +33,9 @@
#include "sandybridge.h"
#include <cpu/intel/smm/gen1/smi.h>
-static int bridge_revision_id = -1;
-
/* IGD UMA memory */
static uint64_t uma_memory_base = 0;
static uint64_t uma_memory_size = 0;
-
-int bridge_silicon_revision(void)
-{
- if (bridge_revision_id < 0) {
- uint8_t stepping = cpuid_eax(1) & 0xf;
- uint8_t bridge_id = pci_read_config16(
- dev_find_slot(0, PCI_DEVFN(0, 0)),
- PCI_DEVICE_ID) & 0xf0;
- bridge_revision_id = bridge_id | stepping;
- }
- return bridge_revision_id;
-}
/* Reserve everything between A segment and 1MB:
*
@@ -106,7 +92,7 @@
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
#endif
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ if (is_sandy_bridge_cpu()) {
/* Required for SandyBridge sighting 3715511 */
bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
@@ -307,7 +293,7 @@
DMIBAR32(0x1d0) = 0xffffffff;
/* Steps prior to DMI ASPM */
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ if (is_sandy_bridge_cpu()) {
reg32 = DMIBAR32(0x250);
reg32 &= ~((1 << 22)|(1 << 20));
reg32 |= (1 << 21);
@@ -334,7 +320,7 @@
}
/* Enable ASPM on SNB link, should happen before PCH link */
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ if (is_sandy_bridge_cpu()) {
reg32 = DMIBAR32(0xd04);
reg32 |= (1 << 4);
DMIBAR32(0xd04) = reg32;
@@ -410,7 +396,7 @@
bridge_type = MCHBAR32(0x5f10);
bridge_type &= ~0xff;
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ if (!is_sandy_bridge_cpu()) {
/* Enable Power Aware Interrupt Routing */
u8 pair = MCHBAR8(0x5418);
pair &= ~0xf; /* Clear 3:0 */
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index c0cb9a4..4c500e4 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -298,7 +298,7 @@
static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,
int s3_resume, int me_uma_size)
{
- if (ctrl->sandybridge)
+ if (is_sandy_bridge_cpu())
return try_init_dram_ddr3_sandy(ctrl, fast_boot, s3_resume, me_uma_size);
else
return try_init_dram_ddr3_ivy(ctrl, fast_boot, s3_resume, me_uma_size);
@@ -313,9 +313,7 @@
spd_raw_data spds[4];
struct mrc_data_container *mrc_cache;
ramctr_timing *ctrl_cached;
- struct cpuid_result cpures;
int err;
- u32 cpu;
MCHBAR32(0x5f00) |= 1;
@@ -395,11 +393,6 @@
memset(&ctrl, 0, sizeof(ctrl));
ctrl.tCK = min_tck;
- /* Get architecture */
- cpures = cpuid(1);
- cpu = cpures.eax;
- ctrl.sandybridge = IS_SANDY_CPU(cpu);
-
/* Get DDR3 SPD data */
memset(spds, 0, sizeof(spds));
mainboard_get_spd(spds, 0);
@@ -416,11 +409,6 @@
/* Reset internal state */
memset(&ctrl, 0, sizeof(ctrl));
ctrl.tCK = min_tck;
-
- /* Get architecture */
- cpures = cpuid(1);
- cpu = cpures.eax;
- ctrl.sandybridge = IS_SANDY_CPU(cpu);
/* Reset DDR3 frequency */
dram_find_spds_ddr3(spds, &ctrl);
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index f08fc38..1eb5b6f 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -25,7 +25,6 @@
#include <northbridge/intel/sandybridge/chip.h>
#include <device/pci_def.h>
#include <delay.h>
-#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include "raminit_native.h"
#include "raminit_common.h"
@@ -191,15 +190,13 @@
static void dram_odt_stretch(ramctr_timing *ctrl, int channel)
{
- struct cpuid_result cpures;
- u32 reg, addr, cpu, stretch;
+ u32 reg, addr, stretch;
stretch = ctrl->ref_card_offset[channel];
/* ODT stretch: Delay ODT signal by stretch value.
* Useful for multi DIMM setups on the same channel. */
- cpures = cpuid(1);
- cpu = cpures.eax;
- if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) {
+
+ if (is_sandy_bridge_cpu() && bridge_silicon_revision() >= SNB_STEP_C) {
if (stretch == 2)
stretch = 3;
addr = 0x400 * channel + 0x401c;
@@ -382,7 +379,6 @@
unsigned int get_mem_min_tck(void)
{
u32 reg32;
- u8 rev;
const struct device *dev;
const struct northbridge_intel_sandybridge_config *cfg = NULL;
@@ -395,9 +391,7 @@
if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
return TCK_1333MHZ;
- rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
-
- if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
+ if (is_sandy_bridge_cpu()) {
/* read Capabilities A Register DMFC bits */
reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A);
reg32 &= 0x7;
@@ -3107,12 +3101,8 @@
void set_4f8c(void)
{
- struct cpuid_result cpures;
- u32 cpu;
-
- cpures = cpuid(1);
- cpu = (cpures.eax);
- if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) {
+ if (is_sandy_bridge_cpu() && (bridge_silicon_revision() >= SNB_STEP_D0
+ || bridge_silicon_revision() == SNB_STEP_D1)) {
MCHBAR32(0x4f8c) = 0x141D1519;
} else {
MCHBAR32(0x4f8c) = 0x551D1519;
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index 6ce2453..4770e60 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -21,18 +21,6 @@
#define BASEFREQ 133
#define tDLLK 512
-#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0)
-#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4)
-#define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5)
-#define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6)
-#define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7)
-
-#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0)
-#define IS_IVY_CPU_C(x) ((x & 0xf) == 4)
-#define IS_IVY_CPU_K(x) ((x & 0xf) == 5)
-#define IS_IVY_CPU_D(x) ((x & 0xf) == 6)
-#define IS_IVY_CPU_E(x) ((x & 0xf) >= 8)
-
#define NUM_CHANNELS 2
#define NUM_SLOTRANKS 4
#define NUM_SLOTS 2
@@ -75,7 +63,6 @@
typedef struct ramctr_timing_st {
u16 spd_crc[NUM_CHANNELS][NUM_SLOTS];
- int sandybridge;
/* DDR base_freq = 100 Mhz / 133 Mhz */
u8 base_freq;
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 41fef22..5f8e4e2 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -23,6 +23,7 @@
#define BASE_REV_MASK 0x50
/* SandyBridge CPU stepping */
+#define SNB_STEP_C (BASE_REV_SNB + 4)
#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */
#define SNB_STEP_D1 (BASE_REV_SNB + 6)
#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */
@@ -207,7 +208,6 @@
#ifdef __SMM__
void intel_sandybridge_finalize_smm(void);
#else /* !__SMM__ */
-int bridge_silicon_revision(void);
void sandybridge_early_initialization(void);
void sandybridge_init_iommu(void);
void sandybridge_late_initialization(void);
@@ -230,7 +230,8 @@
int mainboard_should_reset_usb(int s3resume);
void perform_raminit(int s3resume);
enum platform_type get_platform_type(void);
-
+int bridge_silicon_revision(void);
+int is_sandy_bridge_cpu(void);
#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
--
To view, visit https://review.coreboot.org/22531
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iba342dc1830102f3751c89c2b5736f4477c9f4e4
Gerrit-Change-Number: 22531
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
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