<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22531">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/sandybridge: Use bridge_silicon_revision in all places<br><br>* Move bridge_silicon_revision to common.c<br>* Use bridge_silicon_revision instead of custom methods<br>* Get rid of unused macros<br><br>Change-Id: Iba342dc1830102f3751c89c2b5736f4477c9f4e4<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M src/northbridge/intel/sandybridge/common.c<br>M src/northbridge/intel/sandybridge/gma.c<br>M src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c<br>M src/northbridge/intel/sandybridge/northbridge.c<br>M src/northbridge/intel/sandybridge/raminit.c<br>M src/northbridge/intel/sandybridge/raminit_common.c<br>M src/northbridge/intel/sandybridge/raminit_common.h<br>M src/northbridge/intel/sandybridge/sandybridge.h<br>8 files changed, 41 insertions(+), 70 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/22531/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c<br>index b5a3544..059dc1e 100644<br>--- a/src/northbridge/intel/sandybridge/common.c<br>+++ b/src/northbridge/intel/sandybridge/common.c<br>@@ -38,3 +38,23 @@<br> return platform_mobile;<br> }<br> }<br>+<br>+int bridge_silicon_revision(void)<br>+{<br>+ const uint8_t stepping = cpuid_eax(1) & 0xf;<br>+<br>+ const uint8_t bridge_id = pci_read_config16(<br>+#if defined(__SIMPLE_DEVICE__)<br>+ PCI_DEVFN(0, 0),<br>+#else<br>+ dev_find_slot(0, PCI_DEVFN(0, 0)),<br>+#endif<br>+ PCI_DEVICE_ID) & 0xf0;<br>+<br>+ return bridge_id | stepping;<br>+}<br>+<br>+int is_sandy_bridge_cpu(void)<br>+{<br>+ return (bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB;<br>+}<br>diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c<br>index 61b9008..3ec660d 100644<br>--- a/src/northbridge/intel/sandybridge/gma.c<br>+++ b/src/northbridge/intel/sandybridge/gma.c<br>@@ -348,7 +348,7 @@<br> gtt_poll(0x130040, (1 << 0), (1 << 0));<br> }<br> <br>- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {<br>+ if (is_sandy_bridge_cpu()) {<br> /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */<br> reg32 = gtt_read(0x42004);<br> reg32 |= (1 << 14) | (1 << 15);<br>@@ -364,7 +364,7 @@<br> <br> /* 2: Get GT SKU from GTT+0x911c[13] */<br> reg32 = gtt_read(0x911c);<br>- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {<br>+ if (is_sandy_bridge_cpu()) {<br> if (reg32 & (1 << 13)) {<br> printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n");<br> gtt_write_powermeter(snb_pm_gt1);<br>@@ -421,8 +421,8 @@<br> gtt_write(0xa180, reg32);<br> <br> /* 6a: for SnB step D2+ only */<br>- if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&<br>- (bridge_silicon_revision() >= SNB_STEP_D2)) {<br>+ if (is_sandy_bridge_cpu() &&<br>+ (bridge_silicon_revision() >= SNB_STEP_D2)) {<br> reg32 = gtt_read(0x9400);<br> reg32 |= (1 << 7);<br> gtt_write(0x9400, reg32);<br>@@ -434,7 +434,7 @@<br> gtt_poll(0x941c, (1 << 1), (0 << 1));<br> }<br> <br>- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {<br>+ if (!is_sandy_bridge_cpu()) {<br> reg32 = gtt_read(0x907c);<br> reg32 |= (1 << 16);<br> gtt_write(0x907c, reg32);<br>@@ -485,7 +485,7 @@<br> gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */<br> <br> /* 11a: Enable Render Standby (RC6) */<br>- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {<br>+ if (!is_sandy_bridge_cpu()) {<br> /*<br> * IvyBridge should also support DeepRenderStandby.<br> *<br>diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c<br>index 5e8c188..742264d 100644<br>--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c<br>+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c<br>@@ -133,9 +133,8 @@<br> if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))<br> return 0;<br> <br>- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {<br>+ if (!is_sandy_bridge_cpu())<br> return i915lightup_ivy(info, physbase, piobase, mmio, lfb);<br>- }<br> <br> write32(mmio + 0x00070080, 0x00000000);<br> write32(mmio + DSPCNTR(0), 0x00000000);<br>diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c<br>index 9fed17e..66cf7b4 100644<br>--- a/src/northbridge/intel/sandybridge/northbridge.c<br>+++ b/src/northbridge/intel/sandybridge/northbridge.c<br>@@ -33,23 +33,9 @@<br> #include "sandybridge.h"<br> #include <cpu/intel/smm/gen1/smi.h><br> <br>-static int bridge_revision_id = -1;<br>-<br> /* IGD UMA memory */<br> static uint64_t uma_memory_base = 0;<br> static uint64_t uma_memory_size = 0;<br>-<br>-int bridge_silicon_revision(void)<br>-{<br>- if (bridge_revision_id < 0) {<br>- uint8_t stepping = cpuid_eax(1) & 0xf;<br>- uint8_t bridge_id = pci_read_config16(<br>- dev_find_slot(0, PCI_DEVFN(0, 0)),<br>- PCI_DEVICE_ID) & 0xf0;<br>- bridge_revision_id = bridge_id | stepping;<br>- }<br>- return bridge_revision_id;<br>-}<br> <br> /* Reserve everything between A segment and 1MB:<br> *<br>@@ -106,7 +92,7 @@<br> CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);<br> #endif<br> <br>- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {<br>+ if (is_sandy_bridge_cpu()) {<br> /* Required for SandyBridge sighting 3715511 */<br> bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);<br> bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);<br>@@ -307,7 +293,7 @@<br> DMIBAR32(0x1d0) = 0xffffffff;<br> <br> /* Steps prior to DMI ASPM */<br>- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {<br>+ if (is_sandy_bridge_cpu()) {<br> reg32 = DMIBAR32(0x250);<br> reg32 &= ~((1 << 22)|(1 << 20));<br> reg32 |= (1 << 21);<br>@@ -334,7 +320,7 @@<br> }<br> <br> /* Enable ASPM on SNB link, should happen before PCH link */<br>- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {<br>+ if (is_sandy_bridge_cpu()) {<br> reg32 = DMIBAR32(0xd04);<br> reg32 |= (1 << 4);<br> DMIBAR32(0xd04) = reg32;<br>@@ -410,7 +396,7 @@<br> bridge_type = MCHBAR32(0x5f10);<br> bridge_type &= ~0xff;<br> <br>- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {<br>+ if (!is_sandy_bridge_cpu()) {<br> /* Enable Power Aware Interrupt Routing */<br> u8 pair = MCHBAR8(0x5418);<br> pair &= ~0xf; /* Clear 3:0 */<br>diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c<br>index c0cb9a4..4c500e4 100644<br>--- a/src/northbridge/intel/sandybridge/raminit.c<br>+++ b/src/northbridge/intel/sandybridge/raminit.c<br>@@ -298,7 +298,7 @@<br> static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,<br> int s3_resume, int me_uma_size)<br> {<br>- if (ctrl->sandybridge)<br>+ if (is_sandy_bridge_cpu())<br> return try_init_dram_ddr3_sandy(ctrl, fast_boot, s3_resume, me_uma_size);<br> else<br> return try_init_dram_ddr3_ivy(ctrl, fast_boot, s3_resume, me_uma_size);<br>@@ -313,9 +313,7 @@<br> spd_raw_data spds[4];<br> struct mrc_data_container *mrc_cache;<br> ramctr_timing *ctrl_cached;<br>- struct cpuid_result cpures;<br> int err;<br>- u32 cpu;<br> <br> MCHBAR32(0x5f00) |= 1;<br> <br>@@ -395,11 +393,6 @@<br> memset(&ctrl, 0, sizeof(ctrl));<br> ctrl.tCK = min_tck;<br> <br>- /* Get architecture */<br>- cpures = cpuid(1);<br>- cpu = cpures.eax;<br>- ctrl.sandybridge = IS_SANDY_CPU(cpu);<br>-<br> /* Get DDR3 SPD data */<br> memset(spds, 0, sizeof(spds));<br> mainboard_get_spd(spds, 0);<br>@@ -416,11 +409,6 @@<br> /* Reset internal state */<br> memset(&ctrl, 0, sizeof(ctrl));<br> ctrl.tCK = min_tck;<br>-<br>- /* Get architecture */<br>- cpures = cpuid(1);<br>- cpu = cpures.eax;<br>- ctrl.sandybridge = IS_SANDY_CPU(cpu);<br> <br> /* Reset DDR3 frequency */<br> dram_find_spds_ddr3(spds, &ctrl);<br>diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c<br>index f08fc38..1eb5b6f 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_common.c<br>+++ b/src/northbridge/intel/sandybridge/raminit_common.c<br>@@ -25,7 +25,6 @@<br> #include <northbridge/intel/sandybridge/chip.h><br> #include <device/pci_def.h><br> #include <delay.h><br>-#include <arch/cpu.h><br> #include <cpu/x86/msr.h><br> #include "raminit_native.h"<br> #include "raminit_common.h"<br>@@ -191,15 +190,13 @@<br> <br> static void dram_odt_stretch(ramctr_timing *ctrl, int channel)<br> {<br>- struct cpuid_result cpures;<br>- u32 reg, addr, cpu, stretch;<br>+ u32 reg, addr, stretch;<br> <br> stretch = ctrl->ref_card_offset[channel];<br> /* ODT stretch: Delay ODT signal by stretch value.<br> * Useful for multi DIMM setups on the same channel. */<br>- cpures = cpuid(1);<br>- cpu = cpures.eax;<br>- if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) {<br>+<br>+ if (is_sandy_bridge_cpu() && bridge_silicon_revision() >= SNB_STEP_C) {<br> if (stretch == 2)<br> stretch = 3;<br> addr = 0x400 * channel + 0x401c;<br>@@ -382,7 +379,6 @@<br> unsigned int get_mem_min_tck(void)<br> {<br> u32 reg32;<br>- u8 rev;<br> const struct device *dev;<br> const struct northbridge_intel_sandybridge_config *cfg = NULL;<br> <br>@@ -395,9 +391,7 @@<br> if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))<br> return TCK_1333MHZ;<br> <br>- rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);<br>-<br>- if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {<br>+ if (is_sandy_bridge_cpu()) {<br> /* read Capabilities A Register DMFC bits */<br> reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A);<br> reg32 &= 0x7;<br>@@ -3107,12 +3101,8 @@<br> <br> void set_4f8c(void)<br> {<br>- struct cpuid_result cpures;<br>- u32 cpu;<br>-<br>- cpures = cpuid(1);<br>- cpu = (cpures.eax);<br>- if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) {<br>+ if (is_sandy_bridge_cpu() && (bridge_silicon_revision() >= SNB_STEP_D0<br>+ || bridge_silicon_revision() == SNB_STEP_D1)) {<br> MCHBAR32(0x4f8c) = 0x141D1519;<br> } else {<br> MCHBAR32(0x4f8c) = 0x551D1519;<br>diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h<br>index 6ce2453..4770e60 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_common.h<br>+++ b/src/northbridge/intel/sandybridge/raminit_common.h<br>@@ -21,18 +21,6 @@<br> #define BASEFREQ 133<br> #define tDLLK 512<br> <br>-#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0)<br>-#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4)<br>-#define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5)<br>-#define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6)<br>-#define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7)<br>-<br>-#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0)<br>-#define IS_IVY_CPU_C(x) ((x & 0xf) == 4)<br>-#define IS_IVY_CPU_K(x) ((x & 0xf) == 5)<br>-#define IS_IVY_CPU_D(x) ((x & 0xf) == 6)<br>-#define IS_IVY_CPU_E(x) ((x & 0xf) >= 8)<br>-<br> #define NUM_CHANNELS 2<br> #define NUM_SLOTRANKS 4<br> #define NUM_SLOTS 2<br>@@ -75,7 +63,6 @@<br> <br> typedef struct ramctr_timing_st {<br> u16 spd_crc[NUM_CHANNELS][NUM_SLOTS];<br>- int sandybridge;<br> <br> /* DDR base_freq = 100 Mhz / 133 Mhz */<br> u8 base_freq;<br>diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h<br>index 41fef22..5f8e4e2 100644<br>--- a/src/northbridge/intel/sandybridge/sandybridge.h<br>+++ b/src/northbridge/intel/sandybridge/sandybridge.h<br>@@ -23,6 +23,7 @@<br> #define BASE_REV_MASK 0x50<br> <br> /* SandyBridge CPU stepping */<br>+#define SNB_STEP_C (BASE_REV_SNB + 4)<br> #define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */<br> #define SNB_STEP_D1 (BASE_REV_SNB + 6)<br> #define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */<br>@@ -207,7 +208,6 @@<br> #ifdef __SMM__<br> void intel_sandybridge_finalize_smm(void);<br> #else /* !__SMM__ */<br>-int bridge_silicon_revision(void);<br> void sandybridge_early_initialization(void);<br> void sandybridge_init_iommu(void);<br> void sandybridge_late_initialization(void);<br>@@ -230,7 +230,8 @@<br> int mainboard_should_reset_usb(int s3resume);<br> void perform_raminit(int s3resume);<br> enum platform_type get_platform_type(void);<br>-<br>+int bridge_silicon_revision(void);<br>+int is_sandy_bridge_cpu(void);<br> #if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)<br> #include <device/device.h><br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/22531">change 22531</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22531"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iba342dc1830102f3751c89c2b5736f4477c9f4e4 </div>
<div style="display:none"> Gerrit-Change-Number: 22531 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>