[coreboot-gerrit] Change in coreboot[master]: google/kahlee/variant/grunt: Add SPD function
Marc Jones (Code Review)
gerrit at coreboot.org
Fri Nov 17 02:58:20 CET 2017
Marc Jones has uploaded this change for review. ( https://review.coreboot.org/22486
Change subject: google/kahlee/variant/grunt: Add SPD function
......................................................................
google/kahlee/variant/grunt: Add SPD function
Grunt has soldered down memory and stores the SPD in cbfs.
BUG=b:67845441
Change-Id: I789002bfadc1a2b24f9046708986d29c0e2daf33
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/mainboard/google/kahlee/Kconfig
A src/mainboard/google/kahlee/variants/grunt/Makefile.inc
A src/mainboard/google/kahlee/variants/grunt/gpio.c
A src/mainboard/google/kahlee/variants/grunt/memory.c
A src/mainboard/google/kahlee/variants/grunt/spd/Makefile.inc
A src/mainboard/google/kahlee/variants/grunt/spd/empty.spd.hex
6 files changed, 287 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/22486/1
diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig
index 7173f1d..6fe6f11 100644
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@@ -22,6 +22,7 @@
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_OPTION_TABLE
select HAVE_ACPI_TABLES
+ select GENERIC_SPD_BIN
select GFXUMA
select GOOGLE_SMBIOS_MAINBOARD_VERSION
select MAINBOARD_HAS_CHROMEOS
diff --git a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc
new file mode 100644
index 0000000..36a8c4f
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc
@@ -0,0 +1,20 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Google, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+subdirs-y += spd
+
+romstage-y += memory.c
+
+ramstage-y += memory.c
diff --git a/src/mainboard/google/kahlee/variants/grunt/gpio.c b/src/mainboard/google/kahlee/variants/grunt/gpio.c
new file mode 100644
index 0000000..d90a99c
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/grunt/gpio.c
@@ -0,0 +1,150 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <agesawrapper.h>
+#include <baseboard/variants.h>
+#include <soc/smi.h>
+#include <soc/southbridge.h>
+#include <stdlib.h>
+#include <variant/gpio.h>
+
+static const GPIO_CONTROL agesa_board_gpios[] = {
+ /* AGPIO2 PCIE/WLAN WAKE# SCI*/
+ {2, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* SER TX */
+ {8, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+ /* SER RX */
+ {9, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* AGPIO 12 */
+ {12, Function2, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* TS_EN_SOC (TouchScreen enable GPIO) */
+ {13, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+
+ /* CAM_PWRON (Camera enable GPIO) */
+ {14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+
+ /* EC_IN_RW */
+ {15, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* APU_I2C_3_SCL */
+ {19, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* APU_I2C_3_SDA */
+ {20, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* AGPIO22 EC_SCI */
+ {22, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* APU_BT_ON# */
+ {24, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+
+ /* DEVSLP1_SSD */
+ {67, Function1, FCH_GPIO_PULL_UP_ENABLE},
+
+ /* DEVSLP1_EMMC */
+ /* No Connect for now.
+ * {70, Function1, FCH_GPIO_PULL_UP_ENABLE},
+ */
+
+ /* SPI_TPM_CS_L */
+ {76, Function1, FCH_GPIO_PULL_DOWN_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+
+ /* CAM_LED# */
+ {84, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+
+ /* TS_RST# (TouchScreen Reset) */
+ {85, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+
+ /* WLAN_RST#_AUX */
+ {119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+
+ /* BD_ID1 */
+ {135, Function1, 0 },
+
+ /* TPM_SERIRQ# */
+ {139, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* BD_ID2 */
+ {140, Function1, 0 },
+
+ /* APU_SPI_WP */
+ {142, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* BD_ID3 */
+ {144, Function1, 0 },
+
+ {-1}
+};
+
+const GPIO_CONTROL *get_gpio_table(void)
+{
+ return agesa_board_gpios;
+}
+
+/*
+ * GPE setup table must match ACPI GPE ASL
+ * { gevent, gpe, direction, level }
+ */
+static const struct sci_source gpe_table[] = {
+
+ /* EC AGPIO22/Gevent3 -> GPE 3 */
+ {
+ .scimap = 3,
+ .gpe = 3,
+ .direction = SMI_SCI_LVL_LOW,
+ .level = SMI_SCI_EDG,
+ },
+
+ /* PCIE/WLAN AGPIO2/Gevent8 -> GPE8 */
+ {
+ .scimap = 8,
+ .gpe = 8,
+ .direction = SMI_SCI_LVL_LOW,
+ .level = SMI_SCI_LVL,
+ },
+
+ /* EHCI USB_PME -> GPE24 */
+ {
+ .scimap = 24,
+ .gpe = 24,
+ .direction = SMI_SCI_LVL_HIGH,
+ .level = SMI_SCI_LVL,
+ },
+
+ /* XHCIC0 -> GPE31 */
+ {
+ .scimap = 56,
+ .gpe = 31,
+ .direction = SMI_SCI_LVL_HIGH,
+ .level = SMI_SCI_LVL,
+ },
+};
+
+const struct sci_source *get_gpe_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpe_table);
+ return gpe_table;
+}
diff --git a/src/mainboard/google/kahlee/variants/grunt/memory.c b/src/mainboard/google/kahlee/variants/grunt/memory.c
new file mode 100644
index 0000000..99a315b
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/grunt/memory.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <gpio.h> /* src/include/gpio.h */
+#include <spd_bin.h>
+#include <string.h>
+#include <variant/gpio.h>
+#include <amdblocks/dimm_spd.h>
+
+size_t variant_board_id(void)
+{
+ gpio_t pads[] = {
+ [2] = MEM_CONFIG2,
+ [1] = MEM_CONFIG1,
+ [0] = MEM_CONFIG0,
+ };
+
+ return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
+}
+
+int mainboard_read_spd(uint8_t spdAddress, char *buf,
+ size_t len)
+{
+ struct region_device spd_rdev;
+ u8 spd_index = board_id();
+
+ printk(BIOS_INFO, "%s SPD index %d\n", __func__, spd_index);
+
+ if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) {
+ printk(BIOS_ERR, "Error: spd.bin not found\n");
+ return -1;
+ }
+
+ if (len != region_device_sz(&spd_rdev)) {
+ printk(BIOS_ERR, "Error: spd.bin is not the correct size\n");
+ return -1;
+ }
+
+ /* Memory leak is ok since we have memory mapped boot media */
+ memcpy(buf, rdev_mmap_full(&spd_rdev), len);
+ return 0;
+}
diff --git a/src/mainboard/google/kahlee/variants/grunt/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/grunt/spd/Makefile.inc
new file mode 100644
index 0000000..c199629
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/grunt/spd/Makefile.inc
@@ -0,0 +1,26 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+## Copyright (C) 2015 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
+
+SPD_SOURCES = empty # 0b000
+SPD_SOURCES += empty # 1b001
+SPD_SOURCES += empty # 2b010
+SPD_SOURCES += empty # 3b011
+SPD_SOURCES += empty # 4b100
+SPD_SOURCES += empty # 5b101
+SPD_SOURCES += empty # 6b110
+SPD_SOURCES += empty # 7b111
diff --git a/src/mainboard/google/kahlee/variants/grunt/spd/empty.spd.hex b/src/mainboard/google/kahlee/variants/grunt/spd/empty.spd.hex
new file mode 100644
index 0000000..67b46cd
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/grunt/spd/empty.spd.hex
@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
--
To view, visit https://review.coreboot.org/22486
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I789002bfadc1a2b24f9046708986d29c0e2daf33
Gerrit-Change-Number: 22486
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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