[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Fix SPD files and functions camel case
Marc Jones (Code Review)
gerrit at coreboot.org
Fri Nov 17 02:58:18 CET 2017
Marc Jones has uploaded this change for review. ( https://review.coreboot.org/22483
Change subject: amd/stoneyridge: Fix SPD files and functions camel case
......................................................................
amd/stoneyridge: Fix SPD files and functions camel case
Remove ugly camel case in the soc/amd/common and Stoney Ridge
SPD files and functions. Update the related mainboards.
Also, remove a unreferenced function prototype, smbus_readSpd().
Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/mainboard/amd/gardenia/devicetree.cb
M src/mainboard/google/kahlee/variants/kahlee/devicetree.cb
R src/soc/amd/common/block/include/amdblocks/dimm_spd.h
M src/soc/amd/stoneyridge/BiosCallOuts.c
M src/soc/amd/stoneyridge/Makefile.inc
M src/soc/amd/stoneyridge/chip.h
R src/soc/amd/stoneyridge/dimm_spd.c
M src/soc/amd/stoneyridge/smbus_spd.c
8 files changed, 23 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/22483/1
diff --git a/src/mainboard/amd/gardenia/devicetree.cb b/src/mainboard/amd/gardenia/devicetree.cb
index 38bf86f..e9946ad 100644
--- a/src/mainboard/amd/gardenia/devicetree.cb
+++ b/src/mainboard/amd/gardenia/devicetree.cb
@@ -14,7 +14,7 @@
#
chip soc/amd/stoneyridge
- register "spdAddrLookup" = "
+ register "spd_addr_lookup" = "
{
{ {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1
}"
diff --git a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb
index 28f22a4..409e09e 100644
--- a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb
@@ -14,7 +14,7 @@
#
chip soc/amd/stoneyridge
- register "spdAddrLookup" = "
+ register "spd_addr_lookup" = "
{
{ {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0
}"
diff --git a/src/soc/amd/common/dimmSpd.h b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h
similarity index 79%
rename from src/soc/amd/common/dimmSpd.h
rename to src/soc/amd/common/block/include/amdblocks/dimm_spd.h
index 9abdb98..8683caa 100644
--- a/src/soc/amd/common/dimmSpd.h
+++ b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,7 +20,6 @@
AmdMemoryReadSPD(IN UINT32 Func, IN UINTN Data,
IN OUT AGESA_READ_SPD_PARAMS *SpdData);
-int sb_readSpd(uint8_t spdAddress, char *buf, size_t len);
-int smbus_readSpd(int spdAddress, char *buf, size_t len);
+int sb_read_spd(uint8_t spdAddress, char *buf, size_t len);
#endif
diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c
index 9110338..2c68f38 100644
--- a/src/soc/amd/stoneyridge/BiosCallOuts.c
+++ b/src/soc/amd/stoneyridge/BiosCallOuts.c
@@ -21,7 +21,7 @@
#include <agesawrapper.h>
#include <amdlib.h>
-#include <dimmSpd.h>
+#include <amdblocks/dimm_spd.h>
AGESA_STATUS agesa_fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
{
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 197145a..8b1c648 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -47,7 +47,7 @@
romstage-y += BiosCallOuts.c
romstage-y += romstage.c
romstage-y += early_setup.c
-romstage-y += dimmSpd.c
+romstage-y += dimm_spd.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
romstage-y += gpio.c
romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index f50851b..5688a73 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -25,7 +25,7 @@
#define MAX_DIMMS_PER_CH 2
struct soc_amd_stoneyridge_config {
- u8 spdAddrLookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH];
+ u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH];
enum {
DRAM_CONTENTS_KEEP,
DRAM_CONTENTS_CLEAR
diff --git a/src/soc/amd/stoneyridge/dimmSpd.c b/src/soc/amd/stoneyridge/dimm_spd.c
similarity index 73%
rename from src/soc/amd/stoneyridge/dimmSpd.c
rename to src/soc/amd/stoneyridge/dimm_spd.c
index 163779d..13fd72f 100644
--- a/src/soc/amd/stoneyridge/dimmSpd.c
+++ b/src/soc/amd/stoneyridge/dimm_spd.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 - 2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,28 +19,28 @@
#include <soc/pci_devs.h>
#include <stdlib.h>
#include "chip.h"
-#include <dimmSpd.h>
+#include <amdblocks/dimm_spd.h>
AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2,
AGESA_READ_SPD_PARAMS *info)
{
- uint8_t spdAddress;
+ uint8_t spd_address;
DEVTREE_CONST struct device *dev = dev_find_slot(0, DCT_DEVFN);
DEVTREE_CONST struct soc_amd_stoneyridge_config *conf = dev->chip_info;
if ((dev == 0) || (conf == 0))
return AGESA_ERROR;
- if (info->SocketId >= ARRAY_SIZE(conf->spdAddrLookup))
+ if (info->SocketId >= ARRAY_SIZE(conf->spd_addr_lookup))
return AGESA_ERROR;
- if (info->MemChannelId >= ARRAY_SIZE(conf->spdAddrLookup[0]))
+ if (info->MemChannelId >= ARRAY_SIZE(conf->spd_addr_lookup[0]))
return AGESA_ERROR;
- if (info->DimmId >= ARRAY_SIZE(conf->spdAddrLookup[0][0]))
+ if (info->DimmId >= ARRAY_SIZE(conf->spd_addr_lookup[0][0]))
return AGESA_ERROR;
- spdAddress = conf->spdAddrLookup
+ spd_address = conf->spd_addr_lookup
[info->SocketId][info->MemChannelId][info->DimmId];
- if (spdAddress == 0)
+ if (spd_address == 0)
return AGESA_ERROR;
- int err = sb_readSpd(spdAddress, (void *)info->Buffer, 128);
+ int err = sb_read_spd(spd_address, (void *)info->Buffer, 128);
if (err)
return AGESA_ERROR;
return AGESA_SUCCESS;
diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c
index f5c77c9..acd907e 100644
--- a/src/soc/amd/stoneyridge/smbus_spd.c
+++ b/src/soc/amd/stoneyridge/smbus_spd.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
#include <device/device.h>
#include <soc/southbridge.h>
#include <soc/smbus.h>
-#include <dimmSpd.h>
+#include <amdblocks/dimm_spd.h>
/*
* readspd - Read one or more SPD bytes from a DIMM.
@@ -72,24 +72,24 @@
return 0;
}
-static void writePmReg(int reg, int data)
+static void write_pm_reg(int reg, int data)
{
outb(reg, PM_INDEX);
outb(data, PM_DATA);
}
-static void setupFch(uint16_t ioBase)
+static void setup_fch(uint16_t ioBase)
{
- writePmReg(SMB_ASF_IO_BASE, ioBase >> 8);
+ write_pm_reg(SMB_ASF_IO_BASE, ioBase >> 8);
outb(SMB_SPEED_400KHZ, ioBase + SMBTIMING);
/* Clear all SMBUS status bits */
outb(SMBHST_STAT_CLEAR, ioBase + SMBHSTSTAT);
outb(SMBSLV_STAT_CLEAR, ioBase + SMBSLVSTAT);
}
-int sb_readSpd(uint8_t spdAddress, char *buf, size_t len)
+int sb_read_spd(uint8_t spdAddress, char *buf, size_t len)
{
uint16_t ioBase = SMB_BASE_ADDR;
- setupFch(ioBase);
+ setup_fch(ioBase);
return readspd(ioBase, spdAddress, buf, len);
}
--
To view, visit https://review.coreboot.org/22483
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea
Gerrit-Change-Number: 22483
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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