[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add GPIO community 3 definition
Lijian Zhao (Code Review)
gerrit at coreboot.org
Fri Nov 17 01:15:34 CET 2017
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/22482
Change subject: soc/intel/cannonlake: Add GPIO community 3 definition
......................................................................
soc/intel/cannonlake: Add GPIO community 3 definition
Fill the missing GPIO definition of community 3.
Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/gpio.c
M src/soc/intel/cannonlake/include/soc/gpio_defs.h
M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
3 files changed, 141 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/22482/1
diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c
index 0cc4164..67021e5 100644
--- a/src/soc/intel/cannonlake/gpio.c
+++ b/src/soc/intel/cannonlake/gpio.c
@@ -32,10 +32,10 @@
};
static const struct pad_community cnl_communities[] = {
- { /* GPP A, B, G */
+ { /* GPP A, B, G, SPI */
.port = PID_GPIOCOM0,
.first_pad = GPP_A0,
- .last_pad = GPP_G7,
+ .last_pad = SPI0_CLK_LOOPBK,
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -46,10 +46,10 @@
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map_com0,
.num_reset_vals = ARRAY_SIZE(rst_map_com0),
- }, { /* GPP D, F, H */
+ }, { /* GPP D, F, H, VGPIO */
.port = PID_GPIOCOM1,
.first_pad = GPP_D0,
- .last_pad = GPP_H23,
+ .last_pad = VGPIO39,
.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -74,17 +74,31 @@
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
- }, { /* GPP C, E */
- .port = PID_GPIOCOM4,
- .first_pad = GPP_C0,
- .last_pad = GPP_E23,
+ }, { /* AZA, CPU */
+ .port = PID_GPIOCOM3,
+ .first_pad = HDA_BCLK,
+ .last_pad = TRIGGER_OUT,
.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
- .name = "GPP_CE",
+ .name = "GP_AC",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ }, { /* GPP C, E, JTAG, HVMOS */
+ .port = PID_GPIOCOM4,
+ .first_pad = GPP_C0,
+ .last_pad = HVMOS_MLK_RSTB,
+ .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_CEJ",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
index 9c07017..7416bfe 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
@@ -30,13 +30,13 @@
#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
-#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
+#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
#define NUM_GPI_STATUS_REGS \
((NUM_GPIO_COM0_GPI_REGS) +\
(NUM_GPIO_COM1_GPI_REGS) +\
(NUM_GPIO_COM2_GPI_REGS) +\
- (NUM_GPIO_COM3_GPI_REGS))
+ (NUM_GPIO_COM4_GPI_REGS))
/*
* IOxAPIC IRQs for the GPIOs
*/
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
index 0b4ed51..262b28f 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
@@ -18,7 +18,7 @@
#define _SOC_CANNONLAKE_GPIO_SOC_DEFS_H_
/*
- * There are 9 GPIO groups. GPP_A -> GPP_H and GPD. GPD is the special case
+ * There are 15 GPIO groups. GPP_A -> GPP_H and GPD. GPD is the special case
* where that group is not so generic. So most of the fixed numbers and macros
* are based on the GPP groups. The GPIO groups are accessed through register
* blocks called communities.
@@ -32,7 +32,13 @@
#define GPP_C 6
#define GPP_E 7
#define GPD 8
-#define GPIO_NUM_GROUPS 9
+#define GROUP_VGPIO 9
+#define GROUP_SPI A
+#define GROUP_AZA B
+#define GROUP_CPU C
+#define GROUP_JTAG D
+#define GROUP_HVMOS E
+#define GPIO_NUM_GROUPS F
#define GPIO_MAX_NUM_PER_GROUP 24
/*
@@ -101,8 +107,18 @@
#define GPP_G5 56
#define GPP_G6 57
#define GPP_G7 58
+/* Group SPI */
+#define SPI0_IO_2 59
+#define SPI0_IO_3 60
+#define SPI0_MOSI_IO_0 61
+#define SPI0_MOSI_IO_1 62
+#define SPI0_TPM_CSB 63
+#define SPI0_FLASH_0_CSB 64
+#define SPI0_FLASH_1_CSB 65
+#define SPI0_CLK 66
+#define SPI0_CLK_LOOPBK 67
-#define NUM_GPIO_COM0_PADS (GPP_G7 - GPP_A0 + 1)
+#define NUM_GPIO_COM0_PADS (SPI0_CLK_LOOPBK - GPP_A0 + 1)
/* Group D */
#define GPP_D0 68
@@ -180,6 +196,47 @@
#define GPP_H21 138
#define GPP_H22 139
#define GPP_H23 140
+/* Group VGOIO */
+#define VGPIO0 141
+#define VGPIO1 142
+#define VGPIO2 143
+#define VGPIO3 144
+#define VGPIO4 145
+#define VGPIO5 146
+#define VGPIO6 147
+#define VGPIO7 148
+#define VGPIO8 149
+#define VGPIO9 150
+#define VGPIO10 151
+#define VGPIO11 152
+#define VGPIO12 153
+#define VGPIO13 154
+#define VGPIO14 155
+#define VGPIO15 156
+#define VGPIO16 157
+#define VGPIO17 158
+#define VGPIO18 159
+#define VGPIO19 160
+#define VGPIO20 161
+#define VGPIO21 162
+#define VGPIO22 163
+#define VGPIO23 164
+#define VGPIO24 165
+#define VGPIO25 166
+#define VGPIO26 167
+#define VGPIO27 168
+#define VGPIO28 169
+#define VGPIO29 170
+#define VGPIO30 171
+#define VGPIO31 172
+#define VGPIO32 173
+#define VGPIO33 174
+#define VGPIO34 175
+#define VGPIO35 176
+#define VGPIO36 177
+#define VGPIO37 178
+#define VGPIO38 179
+#define VGPIO39 180
#define NUM_GPIO_COM1_PADS (GPP_H23 - GPP_D0 + 1)
@@ -233,24 +290,66 @@
#define GPP_E21 226
#define GPP_E22 227
#define GPP_E23 228
+/* Group Jtag */
+#define JTAG_TDO 229
+#define JTAGX 230
+#define PRDYB 231
+#define PREQB 232
+#define CPU_TRSTB 233
+#define JTAG_TDI 234
+#define JTAG_TMS 235
+#define JTAG_TCK 236
+#define ITP_PMODE 237
+/* Group HVMOS */
+#define HVMOS_L_BKLTEN 238
+#define HVMOS_L_BKLTCTL 239
+#define HVMOS_L_VDDEN 240
+#define HVMOS_SYS_PWROK 241
+#define HVMOS_SYS_RESETB 242
+#define HVMOS_MLK_RSTB 243
-#define NUM_GPIO_COM3_PADS (GPP_E23 - GPP_C0 + 1)
+#define NUM_GPIO_COM4_PADS (HVMOS_MLK_RSTB - GPP_C0 + 1)
/* Group GPD */
-#define GPD0 229
-#define GPD1 230
-#define GPD2 231
-#define GPD3 232
-#define GPD4 233
-#define GPD5 234
-#define GPD6 235
-#define GPD7 236
-#define GPD8 237
-#define GPD9 238
-#define GPD10 239
-#define GPD11 240
+#define GPD0 244
+#define GPD1 245
+#define GPD2 246
+#define GPD3 247
+#define GPD4 248
+#define GPD5 249
+#define GPD6 250
+#define GPD7 251
+#define GPD8 252
+#define GPD9 253
+#define GPD10 254
+#define GPD11 255
#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)
-#define TOTAL_PADS 241
+
+/* Group AZA */
+#define HDA_BCLK 256
+#define HDA_RSTB 257
+#define HDA_SYNC 258
+#define HDA_SDO 259
+#define HDA_SDI_0 260
+#define HDA_SDI_1 261
+#define SSP1_SFRM 262
+#define SSP1_TXD 263
+/* Group CPU */
+#define HDACPU_SDI 264
+#define HDACPU_SDO 265
+#define HDACPU_SCLK 266
+#define PM_SYNC 267
+#define PECI 268
+#define CPUPWRGD 269
+#define THRMTRIPB 270
+#define PLTRST_CPUB 271
+#define PM_DOWN 272
+#define TRIGGER_IN 273
+#define TRIGGER_OUT 274
+
+#define NUM_GPIO_COM3_PADS (TRIGGER_OUT - HDA_BCLK + 1)
+
+#define TOTAL_PADS 275
#endif
--
To view, visit https://review.coreboot.org/22482
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56
Gerrit-Change-Number: 22482
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20171117/540b1515/attachment-0001.html>
More information about the coreboot-gerrit
mailing list