<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22482">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add GPIO community 3 definition<br><br>Fill the missing GPIO definition of community 3.<br><br>Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/gpio.c<br>M src/soc/intel/cannonlake/include/soc/gpio_defs.h<br>M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h<br>3 files changed, 141 insertions(+), 28 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/22482/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c<br>index 0cc4164..67021e5 100644<br>--- a/src/soc/intel/cannonlake/gpio.c<br>+++ b/src/soc/intel/cannonlake/gpio.c<br>@@ -32,10 +32,10 @@<br> };<br> <br> static const struct pad_community cnl_communities[] = {<br>- { /* GPP A, B, G */<br>+ { /* GPP A, B, G, SPI */<br> .port = PID_GPIOCOM0,<br> .first_pad = GPP_A0,<br>- .last_pad = GPP_G7,<br>+ .last_pad = SPI0_CLK_LOOPBK,<br> .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,<br> .pad_cfg_base = PAD_CFG_BASE,<br> .host_own_reg_0 = HOSTSW_OWN_REG_0,<br>@@ -46,10 +46,10 @@<br> .acpi_path = "\\_SB.PCI0.GPIO",<br> .reset_map = rst_map_com0,<br> .num_reset_vals = ARRAY_SIZE(rst_map_com0),<br>- }, { /* GPP D, F, H */<br>+ }, { /* GPP D, F, H, VGPIO */<br> .port = PID_GPIOCOM1,<br> .first_pad = GPP_D0,<br>- .last_pad = GPP_H23,<br>+ .last_pad = VGPIO39,<br> .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,<br> .pad_cfg_base = PAD_CFG_BASE,<br> .host_own_reg_0 = HOSTSW_OWN_REG_0,<br>@@ -74,17 +74,31 @@<br> .acpi_path = "\\_SB.PCI0.GPIO",<br> .reset_map = rst_map,<br> .num_reset_vals = ARRAY_SIZE(rst_map),<br>- }, { /* GPP C, E */<br>- .port = PID_GPIOCOM4,<br>- .first_pad = GPP_C0,<br>- .last_pad = GPP_E23,<br>+ }, { /* AZA, CPU */<br>+ .port = PID_GPIOCOM3,<br>+ .first_pad = HDA_BCLK,<br>+ .last_pad = TRIGGER_OUT,<br> .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,<br> .pad_cfg_base = PAD_CFG_BASE,<br> .host_own_reg_0 = HOSTSW_OWN_REG_0,<br> .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,<br> .gpi_smi_en_reg_0 = GPI_SMI_EN_0,<br> .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,<br>- .name = "GPP_CE",<br>+ .name = "GP_AC",<br>+ .acpi_path = "\\_SB.PCI0.GPIO",<br>+ .reset_map = rst_map,<br>+ .num_reset_vals = ARRAY_SIZE(rst_map),<br>+ }, { /* GPP C, E, JTAG, HVMOS */<br>+ .port = PID_GPIOCOM4,<br>+ .first_pad = GPP_C0,<br>+ .last_pad = HVMOS_MLK_RSTB,<br>+ .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,<br>+ .pad_cfg_base = PAD_CFG_BASE,<br>+ .host_own_reg_0 = HOSTSW_OWN_REG_0,<br>+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,<br>+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,<br>+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,<br>+ .name = "GPP_CEJ",<br> .acpi_path = "\\_SB.PCI0.GPIO",<br> .reset_map = rst_map,<br> .num_reset_vals = ARRAY_SIZE(rst_map),<br>diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h<br>index 9c07017..7416bfe 100644<br>--- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h<br>+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h<br>@@ -30,13 +30,13 @@<br> #define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)<br> #define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)<br> #define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)<br>-#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)<br>+#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)<br> <br> #define NUM_GPI_STATUS_REGS \<br> ((NUM_GPIO_COM0_GPI_REGS) +\<br> (NUM_GPIO_COM1_GPI_REGS) +\<br> (NUM_GPIO_COM2_GPI_REGS) +\<br>- (NUM_GPIO_COM3_GPI_REGS))<br>+ (NUM_GPIO_COM4_GPI_REGS))<br> /*<br> * IOxAPIC IRQs for the GPIOs<br> */<br>diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h<br>index 0b4ed51..262b28f 100644<br>--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h<br>+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h<br>@@ -18,7 +18,7 @@<br> #define _SOC_CANNONLAKE_GPIO_SOC_DEFS_H_<br> <br> /*<br>- * There are 9 GPIO groups. GPP_A -> GPP_H and GPD. GPD is the special case<br>+ * There are 15 GPIO groups. GPP_A -> GPP_H and GPD. GPD is the special case<br> * where that group is not so generic. So most of the fixed numbers and macros<br> * are based on the GPP groups. The GPIO groups are accessed through register<br> * blocks called communities.<br>@@ -32,7 +32,13 @@<br> #define GPP_C 6<br> #define GPP_E 7<br> #define GPD 8<br>-#define GPIO_NUM_GROUPS 9<br>+#define GROUP_VGPIO 9<br>+#define GROUP_SPI A<br>+#define GROUP_AZA B<br>+#define GROUP_CPU C<br>+#define GROUP_JTAG D<br>+#define GROUP_HVMOS E<br>+#define GPIO_NUM_GROUPS F<br> #define GPIO_MAX_NUM_PER_GROUP 24<br> <br> /*<br>@@ -101,8 +107,18 @@<br> #define GPP_G5 56<br> #define GPP_G6 57<br> #define GPP_G7 58<br>+/* Group SPI */<br>+#define SPI0_IO_2 59<br>+#define SPI0_IO_3 60<br>+#define SPI0_MOSI_IO_0 61<br>+#define SPI0_MOSI_IO_1 62<br>+#define SPI0_TPM_CSB 63<br>+#define SPI0_FLASH_0_CSB 64<br>+#define SPI0_FLASH_1_CSB 65<br>+#define SPI0_CLK 66<br>+#define SPI0_CLK_LOOPBK 67<br> <br>-#define NUM_GPIO_COM0_PADS (GPP_G7 - GPP_A0 + 1)<br>+#define NUM_GPIO_COM0_PADS (SPI0_CLK_LOOPBK - GPP_A0 + 1)<br> <br> /* Group D */<br> #define GPP_D0 68<br>@@ -180,6 +196,47 @@<br> #define GPP_H21 138<br> #define GPP_H22 139<br> #define GPP_H23 140<br>+/* Group VGOIO */<br>+#define VGPIO0 141<br>+#define VGPIO1 142<br>+#define VGPIO2 143<br>+#define VGPIO3 144<br>+#define VGPIO4 145<br>+#define VGPIO5 146<br>+#define VGPIO6 147<br>+#define VGPIO7 148<br>+#define VGPIO8 149<br>+#define VGPIO9 150<br>+#define VGPIO10 151<br>+#define VGPIO11 152<br>+#define VGPIO12 153<br>+#define VGPIO13 154<br>+#define VGPIO14 155<br>+#define VGPIO15 156<br>+#define VGPIO16 157<br>+#define VGPIO17 158<br>+#define VGPIO18 159<br>+#define VGPIO19 160<br>+#define VGPIO20 161<br>+#define VGPIO21 162<br>+#define VGPIO22 163<br>+#define VGPIO23 164<br>+#define VGPIO24 165<br>+#define VGPIO25 166<br>+#define VGPIO26 167<br>+#define VGPIO27 168<br>+#define VGPIO28 169<br>+#define VGPIO29 170<br>+#define VGPIO30 171<br>+#define VGPIO31 172<br>+#define VGPIO32 173<br>+#define VGPIO33 174<br>+#define VGPIO34 175<br>+#define VGPIO35 176<br>+#define VGPIO36 177<br>+#define VGPIO37 178<br>+#define VGPIO38 179<br>+#define VGPIO39 180<br> <br> #define NUM_GPIO_COM1_PADS (GPP_H23 - GPP_D0 + 1)<br> <br>@@ -233,24 +290,66 @@<br> #define GPP_E21 226<br> #define GPP_E22 227<br> #define GPP_E23 228<br>+/* Group Jtag */<br>+#define JTAG_TDO 229<br>+#define JTAGX 230<br>+#define PRDYB 231<br>+#define PREQB 232<br>+#define CPU_TRSTB 233<br>+#define JTAG_TDI 234<br>+#define JTAG_TMS 235<br>+#define JTAG_TCK 236<br>+#define ITP_PMODE 237<br>+/* Group HVMOS */<br>+#define HVMOS_L_BKLTEN 238<br>+#define HVMOS_L_BKLTCTL 239<br>+#define HVMOS_L_VDDEN 240<br>+#define HVMOS_SYS_PWROK 241<br>+#define HVMOS_SYS_RESETB 242<br>+#define HVMOS_MLK_RSTB 243<br> <br>-#define NUM_GPIO_COM3_PADS (GPP_E23 - GPP_C0 + 1)<br>+#define NUM_GPIO_COM4_PADS (HVMOS_MLK_RSTB - GPP_C0 + 1)<br> <br> /* Group GPD */<br>-#define GPD0 229<br>-#define GPD1 230<br>-#define GPD2 231<br>-#define GPD3 232<br>-#define GPD4 233<br>-#define GPD5 234<br>-#define GPD6 235<br>-#define GPD7 236<br>-#define GPD8 237<br>-#define GPD9 238<br>-#define GPD10 239<br>-#define GPD11 240<br>+#define GPD0 244<br>+#define GPD1 245<br>+#define GPD2 246<br>+#define GPD3 247<br>+#define GPD4 248<br>+#define GPD5 249<br>+#define GPD6 250<br>+#define GPD7 251<br>+#define GPD8 252<br>+#define GPD9 253<br>+#define GPD10 254<br>+#define GPD11 255<br> <br> #define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)<br> <br>-#define TOTAL_PADS 241<br>+<br>+/* Group AZA */<br>+#define HDA_BCLK 256<br>+#define HDA_RSTB 257<br>+#define HDA_SYNC 258<br>+#define HDA_SDO 259<br>+#define HDA_SDI_0 260<br>+#define HDA_SDI_1 261<br>+#define SSP1_SFRM 262<br>+#define SSP1_TXD 263<br>+/* Group CPU */<br>+#define HDACPU_SDI 264<br>+#define HDACPU_SDO 265<br>+#define HDACPU_SCLK 266<br>+#define PM_SYNC 267<br>+#define PECI 268<br>+#define CPUPWRGD 269<br>+#define THRMTRIPB 270<br>+#define PLTRST_CPUB 271<br>+#define PM_DOWN 272<br>+#define TRIGGER_IN 273<br>+#define TRIGGER_OUT 274<br>+<br>+#define NUM_GPIO_COM3_PADS (TRIGGER_OUT - HDA_BCLK + 1)<br>+<br>+#define TOTAL_PADS 275<br> #endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/22482">change 22482</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22482"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56 </div>
<div style="display:none"> Gerrit-Change-Number: 22482 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>