[coreboot-gerrit] Change in coreboot[master]: soc/intel/kabylake: Add max98357a NHLT blob support

[Naveen Manohar (Code Review)]

Naveen Manohar has uploaded this change for review. ( https://review.coreboot.org/22456


Change subject: soc/intel/kabylake: Add max98357a NHLT blob support
......................................................................

soc/intel/kabylake: Add max98357a NHLT blob support

Add APIs and required parameters for creating max98357a SSP
endpoints in NHLT table.

The use of a NHLT table is required to make audio work
on the kabylake SoCs employing the internal DSP. The table
describes the audio endpoints (render) along with their supported
formats.

BUG=b:68686020
TEST=check that NHLT table for max98357 is created properly

Change-Id: Ia14216c0d0f651541040dea48defcc6f300d3a55
Signed-off-by: Naveen Manohar <naveen.m at intel.com>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/nhlt/Makefile.inc
2 files changed, 16 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/22456/1

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index f66065a..51a49e7 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -231,6 +231,12 @@
 	help
 	  Include DSP firmware settings for 2 channel DMIC array.
 
+config NHLT_DMIC_3CH
+	bool
+	default n
+	help
+	  Include DSP firmware settings for 3 channel DMIC array.
+
 config NHLT_DMIC_4CH
 	bool
 	default n
diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc
index 9c9b4c8..3112ad7 100644
--- a/src/soc/intel/skylake/nhlt/Makefile.inc
+++ b/src/soc/intel/skylake/nhlt/Makefile.inc
@@ -16,6 +16,8 @@
 
 DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin
 DMIC_2CH_48KHZ_32B = dmic-2ch-48khz-32b.bin
+DMIC_3CH_48KHZ_16B = dmic-3ch-48khz-16b.bin
+DMIC_3CH_48KHZ_32B = dmic-3ch-48khz-32b.bin
 DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin
 DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin
 NAU88L25 = nau88l25-2ch-48khz-24b.bin
@@ -36,6 +38,14 @@
 $(DMIC_2CH_48KHZ_32B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_32B)
 $(DMIC_2CH_48KHZ_32B)-type := raw
 
+cbfs-files-$(CONFIG_NHLT_DMIC_3CH) += $(DMIC_3CH_48KHZ_16B)
+$(DMIC_3CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_3CH_48KHZ_16B)
+$(DMIC_3CH_48KHZ_16B)-type := raw
+
+cbfs-files-$(CONFIG_NHLT_DMIC_3CH) += $(DMIC_3CH_48KHZ_32B)
+$(DMIC_3CH_48KHZ_32B)-file := $(NHLT_BLOB_PATH)/$(DMIC_3CH_48KHZ_32B)
+$(DMIC_3CH_48KHZ_32B)-type := raw
+
 cbfs-files-$(CONFIG_NHLT_DMIC_4CH) += $(DMIC_4CH_48KHZ_16B)
 $(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B)
 $(DMIC_4CH_48KHZ_16B)-type := raw

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia14216c0d0f651541040dea48defcc6f300d3a55
Gerrit-Change-Number: 22456
Gerrit-PatchSet: 1
Gerrit-Owner: Naveen Manohar <naveen.m at intel.com>
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