[coreboot-gerrit] Change in coreboot[master]: mb/google/eve: Enable AER and LTR

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/22447


Change subject: mb/google/eve: Enable AER and LTR
......................................................................

mb/google/eve: Enable AER and LTR

AER and LTR must be enabled individually on ports that need it,
in this case it should be enabled for WiFi and NVMe.

BUG=b:65457528
TEST=Wifi team verified that the performance is better with these changes.

Change-Id: I0d688fe07a1f3117c1ca617c2ce78e0d024a3510
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Original-Change-Id: Ib059517fa782ccc18ba5ef1f76058a1898b7bf7a
Original-Signed-off-by: Furquan Shaikh <furquan at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/671211
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj at intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie at google.com>
Original-Commit-Queue: Duncan Laurie <dlaurie at google.com>
Original-Tested-by: Duncan Laurie <dlaurie at google.com>
---
M src/mainboard/google/eve/devicetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/22447/1

diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 069c2b0..3b87fd1 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -143,11 +143,15 @@
 	register "PcieRpEnable[0]" = "1"
 	register "PcieRpClkReqSupport[0]" = "1"
 	register "PcieRpClkReqNumber[0]" = "1"
+	register "PcieRpAdvancedErrorReporting[0]" = "1"
+	register "PcieRpLtrEnable[0]" = "1"
 
 	# Enable Root port 5 with SRCCLKREQ4#
 	register "PcieRpEnable[4]" = "1"
 	register "PcieRpClkReqSupport[4]" = "1"
 	register "PcieRpClkReqNumber[4]" = "4"
+	register "PcieRpAdvancedErrorReporting[4]" = "1"
+	register "PcieRpLtrEnable[4]" = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0d688fe07a1f3117c1ca617c2ce78e0d024a3510
Gerrit-Change-Number: 22447
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
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