<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22447">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/eve: Enable AER and LTR<br><br>AER and LTR must be enabled individually on ports that need it,<br>in this case it should be enabled for WiFi and NVMe.<br><br>BUG=b:65457528<br>TEST=Wifi team verified that the performance is better with these changes.<br><br>Change-Id: I0d688fe07a1f3117c1ca617c2ce78e0d024a3510<br>Signed-off-by: Duncan Laurie <dlaurie@chromium.org><br>Original-Change-Id: Ib059517fa782ccc18ba5ef1f76058a1898b7bf7a<br>Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org><br>Original-Reviewed-on: https://chromium-review.googlesource.com/671211<br>Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com><br>Original-Reviewed-by: Duncan Laurie <dlaurie@google.com><br>Original-Commit-Queue: Duncan Laurie <dlaurie@google.com><br>Original-Tested-by: Duncan Laurie <dlaurie@google.com><br>---<br>M src/mainboard/google/eve/devicetree.cb<br>1 file changed, 4 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/22447/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb<br>index 069c2b0..3b87fd1 100644<br>--- a/src/mainboard/google/eve/devicetree.cb<br>+++ b/src/mainboard/google/eve/devicetree.cb<br>@@ -143,11 +143,15 @@<br>         register "PcieRpEnable[0]" = "1"<br>  register "PcieRpClkReqSupport[0]" = "1"<br>   register "PcieRpClkReqNumber[0]" = "1"<br>+   register "PcieRpAdvancedErrorReporting[0]" = "1"<br>+ register "PcieRpLtrEnable[0]" = "1"<br> <br>    # Enable Root port 5 with SRCCLKREQ4#<br>         register "PcieRpEnable[4]" = "1"<br>  register "PcieRpClkReqSupport[4]" = "1"<br>   register "PcieRpClkReqNumber[4]" = "4"<br>+   register "PcieRpAdvancedErrorReporting[4]" = "1"<br>+ register "PcieRpLtrEnable[4]" = "1"<br> <br>    register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"    # Type-C Port 1<br>       register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"        # Camera<br></pre><p>To view, visit <a href="https://review.coreboot.org/22447">change 22447</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22447"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0d688fe07a1f3117c1ca617c2ce78e0d024a3510 </div>
<div style="display:none"> Gerrit-Change-Number: 22447 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>